1/*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	ipc {
9		cpusec_cpuapp_ipc: ipc-1-2 {
10			compatible = "zephyr,ipc-icmsg";
11			status = "disabled";
12			dcache-alignment = <32>;
13			mboxes = <&cpusec_bellboard 12>,
14				 <&cpuapp_bellboard 0>;
15		};
16
17		cpusec_cpurad_ipc: ipc-1-3 {
18			compatible = "zephyr,ipc-icmsg";
19			status = "disabled";
20			dcache-alignment = <32>;
21			mboxes = <&cpusec_bellboard 18>,
22				 <&cpurad_bellboard 0>;
23		};
24
25		cpuapp_cpurad_ipc: ipc-2-3 {
26			compatible = "zephyr,ipc-icbmsg";
27			dcache-alignment = <32>;
28			status = "disabled";
29			mboxes = <&cpuapp_bellboard 18>,
30				 <&cpurad_bellboard 12>;
31		};
32
33		cpuapp_cpusys_ipc: ipc-2-12 {
34			compatible = "zephyr,ipc-icmsg";
35			status = "disabled";
36			dcache-alignment = <32>;
37			mboxes = <&cpuapp_bellboard 6>,
38				 <&cpusys_vevif 12>;
39		};
40
41		cpuapp_cpuppr_ipc: ipc-2-13 {
42			compatible = "zephyr,ipc-icmsg";
43			status = "disabled";
44			dcache-alignment = <32>;
45			mboxes = <&cpuapp_bellboard 13>,
46				 <&cpuppr_vevif 12>;
47		};
48
49		cpuapp_cpuflpr_ipc: ipc-2-14 {
50			compatible = "zephyr,ipc-icmsg";
51			status = "disabled";
52			dcache-alignment = <32>;
53			mboxes = <&cpuapp_bellboard 14>,
54				 <&cpuflpr_vevif 16>;
55		};
56
57		cpurad_cpusys_ipc: ipc-3-12 {
58			compatible = "zephyr,ipc-icmsg";
59			status = "disabled";
60			dcache-alignment = <32>;
61			mboxes = <&cpurad_bellboard 6>,
62				 <&cpusys_vevif 18>;
63		};
64	};
65};
66