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/Zephyr-Core-3.5.0/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
/Zephyr-Core-3.5.0/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-device.yaml, "jedec,jesd216.yaml"]
9 cs-interval-unit:
13 - 1
14 - 256
20 cs-interval:
28 cs-setup-time:
32 Chip select setup time, in serial clock cycles. See the TCSS field in
36 cs-hold-time:
40 Chip select hold time, in serial clock cycles. See the TCSH field in
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/Zephyr-Core-3.5.0/boards/arm/mimxrt1060_evk/
Dmimxrt1060_evk_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &is25wp064;
13 zephyr,flash-controller = &s26ks512s0;
15 zephyr,code-partition = &slot0_partition;
21 ahb-prefetch;
22 ahb-read-addr-opt;
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
26 combination-mode;
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/Zephyr-Core-3.5.0/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
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/Zephyr-Core-3.5.0/boards/arm/sam4s_xplained/
Dsam4s_xplained.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "sam4s_xplained-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
17 i2c-0 = &twi0;
18 i2c-1 = &twi1;
19 pwm-0 = &pwm0;
28 zephyr,shell-uart = &uart0;
34 compatible = "zephyr,memory-region", "mmio-sram";
37 zephyr,memory-region = "SRAM1";
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6.dts2 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1062_fmurt6-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
25 telem4-gps2 = &lpuart5;
29 zephyr,flash-controller = &s26ks512s0;
31 zephyr,code-partition = &slot0_partition;
36 zephyr,shell-uart = &lpuart7;
41 compatible = "gpio-leds";
42 green_led: led-1 {
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt1050_evk/
Dmimxrt1050_evk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1050_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/display/panel.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "NXP MIMXRT1050-EVK board";
32 zephyr,shell-uart = &lpuart1;
33 zephyr,flash-controller = &s26ks512s0;
35 zephyr,code-partition = &slot0_partition;
40 /* Micron MT48LC16M16A2B4-6AIT:G */
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/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt/
Dflexspi_nor_config.h6 * SPDX-License-Identifier: Apache-2.0
186 /* !< Switch to 0-4-4/0-8-8 mode */
199 /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
201 /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
203 /* !< [0x008-0x00b] Reserved for future use */
205 /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
207 /* !< [0x00d-0x00d] CS hold time, default value: 3 */
209 /* !< [0x00e-0x00e] CS setup time, default value: 3 */
211 /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
214 /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
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/Zephyr-Core-3.5.0/drivers/adc/
Dadc_rpi_pico.c5 * SPDX-License-Identifier: Apache-2.0
24 #define ADC_RPI_CHANNEL_NUM (ADC_CS_RROBIN_MSB - ADC_CS_RROBIN_LSB + 1)
34 /** function pointer to irq setup */
58 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in adc_start_once()
63 return (uint16_t)adc_hw->result; in adc_get_result()
68 return (adc_hw->cs & ADC_CS_ERR_BITS) ? true : false; in adc_get_err()
74 hw_set_bits(&adc_hw->fcs, ADC_FCS_OVER_BITS); in adc_clear_errors()
75 hw_set_bits(&adc_hw->fcs, ADC_FCS_UNDER_BITS); in adc_clear_errors()
76 hw_set_bits(&adc_hw->fcs, ADC_FCS_ERR_BITS); in adc_clear_errors()
77 hw_set_bits(&adc_hw->cs, ADC_CS_ERR_STICKY_BITS); in adc_clear_errors()
[all …]
/Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/
Dmimxrt595_evk_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
34 zephyr,flash-controller = &mx25um51345g;
36 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-Core-3.5.0/subsys/mgmt/ec_host_cmd/backends/
Dec_host_cmd_backend_shi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
26 #define HAL_INSTANCE(dev) (struct shi_reg *)(((const struct shi_npcx_config *)(dev)->config)->base)
42 * This affects the slowest SPI clock we can support. A delay of 8192 us permits a 512-byte request
56 * Space allocation of the past-end status byte (EC_SHI_PAST_END) in the out_msg buffer.
67 * one last past-end byte at the end so any additional bytes clocked out by
75 * overhead, as passed to the host command handler, must be 32-bit aligned.
81 SHI_STATE_NONE = -1,
90 /* Canceling response since CS deasserted and output NOT_READY byte */
106 /* Chip-select interrupts */
154 stat = inst->IBUFSTAT; in shi_npcx_read_buf_pointer()
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/Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio.c2 * Copyright (c) 2016 - 2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
110 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, pdn_gpios, "pdn-gpios");
113 /* CSN is special because it comes from the spi-if property. */
122 "fem node " DT_NODE_PATH(FEM_NODE) " has a spi-if property, "
123 " but the chip select pin is not on the SoC. Check cs-gpios in "
174 NRF_GPIO_PA->DIRSET = BIT(NRF_GPIO_PA_PIN); in radio_setup()
176 NRF_GPIO_PA->OUTSET = BIT(NRF_GPIO_PA_PIN); in radio_setup()
178 NRF_GPIO_PA->OUTCLR = BIT(NRF_GPIO_PA_PIN); in radio_setup()
[all …]
/Zephyr-Core-3.5.0/subsys/bluetooth/controller/ll_sw/
Dull_peripheral.c2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
96 adv = ((struct lll_adv *)ftr->param)->hdr.parent;
97 conn = lll->hdr.parent;
100 pdu_adv = (void *)((struct node_rx_pdu *)rx)->pdu;
102 peer_addr_type = pdu_adv->tx_addr;
103 memcpy(peer_addr, pdu_adv->connect_ind.init_addr, BDADDR_SIZE);
106 uint8_t rl_idx = ftr->rl_idx;
123 link = rx->link;
127 const uint8_t own_id_addr_type = pdu_adv->rx_addr;
[all …]
Dull_central.c2 * Copyright (c) 2018-2021 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
134 lll = &scan->lll; in ll_create_connection()
135 lll_coded = &scan_coded->lll; in ll_create_connection()
144 if (!lll_coded->conn) { in ll_create_connection()
145 lll_coded->conn = lll->conn; in ll_create_connection()
150 if (!lll->conn) { in ll_create_connection()
151 lll->conn = lll_coded->conn; in ll_create_connection()
160 lll = &scan->lll; in ll_create_connection()
164 /* NOTE: non-zero PHY value enables initiating connection on that PHY */ in ll_create_connection()
[all …]
/Zephyr-Core-3.5.0/drivers/spi/
Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
34 /* Device run time data */
57 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
62 return REG8(&regs->RX_FIFO); in rxb_rd8()
86 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
88 regs->MODE = qmode; in qmspi_set_frequency()
128 if (((regs->MODE >> MCHP_QMSPI_M_FDIV_POS) & in qmspi_set_signalling_mode()
134 regs->MODE = (regs->MODE & ~(MCHP_QMSPI_M_SIG_MASK)) in qmspi_set_signalling_mode()
147 switch (config->operation & SPI_LINES_MASK) { in qmspi_config_get_lines()
173 * NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
20 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
34 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
93 /* Device run time data */
122 return -ETIMEDOUT; in xec_qmspi_spin_yield()
132 * Some QMSPI timing register may be modified by the Boot-ROM OTP
143 taps[0] = regs->TM_TAPS; in qmspi_reset()
144 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
145 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_cc13xx_cc26xx_subg.c4 * SPDX-License-Identifier: Apache-2.0
45 /* User-defined CMD_PROP_RADIO_DIV_SETUP structures */
54 /* Radio register overrides for CC13x2R (note: CC26x2 does not support sub-GHz radio)
55 * from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW),
65 /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x3) */
67 /* Tx: Configure PA ramping, set wait time before turning off
73 /* Rx: Set RSSI offset to adjust reported RSSI by -1 dB (default: -2),
77 /* Rx: Set anti-aliasing filter bandwidth to 0x8 (in ADI0, set IFAMPCTL3[7:4]=0x8) */
86 /* CC1352P overrides from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW) */
88 /* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x1) */
[all …]
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.4.rst20 * Added Power Delivery Source Support to the USB-C Stack.
22 * Cache API functions are now fully in-lined by compilers.
23 * Added an API for real-time clocks (RTC).
29 - Introduction of 3 new test harnesses into twister supporting pyTest,
31 - Transitioning to new Ztest API was completed and legacy Ztest was deprecated.
46 * CVE-2023-1901: Under embargo until 2023-07-04
48 * CVE-2023-1902: Under embargo until 2023-07-04
67 +--------------------------------------------------+
69 +--------------------------------------------------+
71 +--------------------------------------------------+
[all …]
Drelease-notes-2.4.rst33 * CVE-2020-10060: UpdateHub Might Dereference An Uninitialized Pointer
34 * CVE-2020-10064: Improper Input Frame Validation in ieee802154 Processing
35 * CVE-2020-10066: Incorrect Error Handling in Bluetooth HCI core
36 * CVE-2020-10072: all threads can access all socket file descriptors
37 * CVE-2020-13598: FS: Buffer Overflow when enabling Long File Names in FAT_FS and calling fs_stat
38 * CVE-2020-13599: Security problem with settings and littlefs
39 * CVE-2020-13601: Under embargo until 2020/11/18
40 * CVE-2020-13602: Remote Denial of Service in LwM2M do_write_op_tlv
50 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
62 * The :c:func:`wdt_feed` function will now return ``-EAGAIN`` if
[all …]
Drelease-notes-3.0.rst22 * CVE-2021-3835: `Zephyr project bug tracker GHSA-fm6v-8625-99jf
23 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-fm6v-8625-99jf>`_
25 * CVE-2021-3861: `Zephyr project bug tracker GHSA-hvfp-w4h8-gxvj
26 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hvfp-w4h8-gxvj>`_
28 * CVE-2021-3966: `Zephyr project bug tracker GHSA-hfxq-3w6x-fv2m
29 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfxq-3w6x-fv2m>`_
36 <https://github.com/zephyrproject-rtos/zephyr/issues?q=is%3Aissue+is%3Aopen+label%3Abug>`_.
53 * Added ``ranges`` and ``dma-ranges`` as invalid property to be used with DT_PROP_LEN()
58 CRC-16-ANSI checksum. A new function, :c:func:`crc16_reflect`, has been
69 * The following Kconfig options related to radio front-end modules (FEMs) were
[all …]
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
/Zephyr-Core-3.5.0/boards/arm/mec15xxevb_assy6853/doc/
Dindex.rst13 MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has
25 - MEC1521HA0SZ ARM Cortex-M4 Processor
26 - 256 KB RAM and 64 KB boot ROM
27 - Keyboard interface
28 - ADC & GPIO headers
29 - UART0, UART1, and UART2
30 - FAN0, FAN1, FAN2 headers
31 - FAN PWM interface
32 - JTAG/SWD, ETM and MCHP Trace ports
33 - PECI interface 3.0
[all …]
/Zephyr-Core-3.5.0/boards/xtensa/esp_wrover_kit/doc/
Dindex.rst3 ESP-WROVER-KIT
9 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
11 ESP-WROVER-KIT features the following integrated components:
13 - ESP32-WROVER-E module
14 - LCD screen
15 - MicroSD card slot
17 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
19 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
20 cost-effective.
32 The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections.
[all …]
/Zephyr-Core-3.5.0/drivers/flash/
Dspi_nor.c2 * Copyright (c) 2018 Savoir-Faire Linux.
8 * SPDX-License-Identifier: Apache-2.0
35 * * Some devices support a Deep Power-Down mode which reduces current
46 * deep-power-down mode.
73 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config)
75 /* Build-time data associated with the device. */
95 /* Expected JEDEC ID, from jedec-id property */
99 /* Optional support for entering 32-bit address mode. */
104 /* Length of BFP structure, in 32-bit words. */
108 * (little-endian stored words), from sfdp-bfp property
[all …]
/Zephyr-Core-3.5.0/drivers/modem/
Dwncm14a2a.c4 * SPDX-License-Identifier: Apache-2.0
80 .cmd_len = (uint16_t)sizeof(cmd_)-1, \
191 while (length--) { in hexdump()
223 for (i = 0; i < (16 - (n % 16)); i++) { in hexdump()
278 sock->context = NULL; in socket_put()
279 sock->socket_id = 0; in socket_put()
280 (void)memset(&sock->src, 0, sizeof(struct sockaddr)); in socket_put()
281 (void)memset(&sock->dst, 0, sizeof(struct sockaddr)); in socket_put()
289 if (addr->sa_family == AF_INET6) { in wncm14a2a_sprint_ip_addr()
290 return net_addr_ntop(AF_INET6, &net_sin6(addr)->sin6_addr, in wncm14a2a_sprint_ip_addr()
[all …]

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