Searched +full:creset +full:- +full:delay +full:- +full:us (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/dts/bindings/fpga/ |
| D | lattice,ice40-fpga-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "lattice,ice40-fpga-base"
8 include: spi-device.yaml
11 cdone-gpios:
12 type: phandle-array
17 cdone-gpios = <&gpio0 0 0>;
18 creset-gpios:
19 type: phandle-array
24 creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);
25 creset-delay-us:
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| /Zephyr-latest/tests/drivers/build_all/fpga/ |
| D | spi.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "lattice,ice40-fpga-bitbang";
14 spi-max-frequency = <1000000>;
16 cdone-gpios = <&test_gpio 0 0>;
17 creset-gpios = <&test_gpio 0 0>;
18 clk-gpios = <&test_gpio 0 0>;
19 pico-gpios = <&test_gpio 0 0>;
20 gpios-set-reg = <0>;
21 gpios-clear-reg = <0>;
22 config-delay-us = <3900>;
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_ice40_bitbang.c | 5 * SPDX-License-Identifier: Apache-2.0
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
56 * This is a calibrated delay loop used to achieve a 1 MHz SPI_CLK frequency
61 * lattice,ice40-fpga.yaml for details.
65 for (; n > 0; --n) { in fpga_ice40_delay()
70 static void fpga_ice40_send_clocks(size_t delay, volatile gpio_port_pins_t *set, in fpga_ice40_send_clocks() argument
73 for (; n > 0; --n) { in fpga_ice40_send_clocks()
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| D | fpga_ice40_spi.c | 4 * SPDX-License-Identifier: Apache-2.0
30 struct fpga_ice40_data *data = dev->data; in fpga_ice40_load()
32 const struct fpga_ice40_config *config = dev->config; in fpga_ice40_load()
35 memcpy(&bus, &config->bus, sizeof(bus)); in fpga_ice40_load()
45 if (data->loaded && crc == data->crc) { in fpga_ice40_load()
46 LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc); in fpga_ice40_load()
49 key = k_spin_lock(&data->lock); in fpga_ice40_load()
52 data->crc = 0; in fpga_ice40_load()
53 data->loaded = false; in fpga_ice40_load()
54 fpga_ice40_crc_to_str(0, data->info); in fpga_ice40_load()
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