4  * SPDX-License-Identifier: Apache-2.0
30 	struct fpga_ice40_data *data = dev->data;  in fpga_ice40_load()
32 	const struct fpga_ice40_config *config = dev->config;  in fpga_ice40_load()
35 	memcpy(&bus, &config->bus, sizeof(bus));  in fpga_ice40_load()
45 	if (data->loaded && crc == data->crc) {  in fpga_ice40_load()
46 		LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc);  in fpga_ice40_load()
49 	key = k_spin_lock(&data->lock);  in fpga_ice40_load()
52 	data->crc = 0;  in fpga_ice40_load()
53 	data->loaded = false;  in fpga_ice40_load()
54 	fpga_ice40_crc_to_str(0, data->info);  in fpga_ice40_load()
57 	ret = gpio_pin_configure_dt(&config->cdone, GPIO_INPUT) ||  in fpga_ice40_load()
58 	      gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load()
59 	      gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
62 	LOG_DBG("Set CRESET low");  in fpga_ice40_load()
63 	ret = gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_LOW);  in fpga_ice40_load()
65 		LOG_ERR("failed to set CRESET low: %d", ret);  in fpga_ice40_load()
70 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_LOW);  in fpga_ice40_load()
77 	LOG_DBG("Delay %u us", config->creset_delay_us);  in fpga_ice40_load()
78 	k_usleep(config->creset_delay_us);  in fpga_ice40_load()
80 	if (gpio_pin_get_dt(&config->cdone) != 0) {  in fpga_ice40_load()
82 		ret = -EIO;  in fpga_ice40_load()
86 	LOG_DBG("Set CRESET high");  in fpga_ice40_load()
87 	ret = gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
89 		LOG_ERR("failed to set CRESET high: %d", ret);  in fpga_ice40_load()
93 	LOG_DBG("Delay %u us", config->config_delay_us);  in fpga_ice40_load()
94 	k_busy_wait(config->config_delay_us);  in fpga_ice40_load()
97 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
103 	LOG_DBG("Send %u clocks", config->leading_clocks);  in fpga_ice40_load()
105 	tx_buf.len = DIV_ROUND_UP(config->leading_clocks, BITS_PER_BYTE);  in fpga_ice40_load()
108 		LOG_ERR("Failed to send leading %u clocks: %d", config->leading_clocks, ret);  in fpga_ice40_load()
113 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_LOW);  in fpga_ice40_load()
129 	ret = gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
135 	LOG_DBG("Send %u clocks", config->trailing_clocks);  in fpga_ice40_load()
137 	tx_buf.len = DIV_ROUND_UP(config->trailing_clocks, BITS_PER_BYTE);  in fpga_ice40_load()
140 		LOG_ERR("Failed to send trailing %u clocks: %d", config->trailing_clocks, ret);  in fpga_ice40_load()
145 	ret = gpio_pin_get_dt(&config->cdone);  in fpga_ice40_load()
150 		ret = -EIO;  in fpga_ice40_load()
156 	data->loaded = true;  in fpga_ice40_load()
157 	fpga_ice40_crc_to_str(crc, data->info);  in fpga_ice40_load()
161 	(void)gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
162 	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
164 	k_spin_unlock(&data->lock, key);  in fpga_ice40_load()