Searched full:configurable (Results 1 – 25 of 192) sorted by relevance
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f105-pll-clock.yaml | 9 pll2, configurable prescaler is used.
52 Configurable prescaler
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| D | st,stm32-clock-mco.yaml | 13 The selected signal goes through a configurable prescaler before output.
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| D | st,stm32f411-plli2s-clock.yaml | 7 Fully configurable I2S dedicated PLL.
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| D | st,stm32f100-pll-clock.yaml | 9 pll2, configurable prescaler is used.
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| D | st,stm32f1-clock-mco.yaml | 12 The STM32F1 MCO is similar to other series but has no configurable
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| /Zephyr-latest/lib/posix/options/ |
| D | Kconfig.profile | 116 This option is not user configurable. It may be configured indirectly by selecting
144 This option is not user configurable. It may be configured indirectly by selecting
161 This option is not user configurable. It may be configured indirectly by selecting
182 This option is not user configurable. It may be configured indirectly by selecting
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| /Zephyr-latest/include/zephyr/drivers/sensor/ |
| D | icm42670.h | 34 * (AAF). The AAF is a filter with fixed coefficients (not user configurable),
38 * filter, with user configurable average filter setting.
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| /Zephyr-latest/dts/bindings/fpga/ |
| D | renesas,slg47115.yaml | 4 description: Renesas SLG47115 GreenPAK Configurable Mixed-Signal IC
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| D | renesas,slg47105.yaml | 4 description: Renesas SLG47105 GreenPAK Configurable Mixed-Signal IC
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| D | renesas,slg471x5.yaml | 4 description: Renesas SLG47105/SLG47115 GreenPAK Configurable Mixed-Signal IC
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| /Zephyr-latest/drivers/mfd/ |
| D | Kconfig.max31790 | 5 bool "Maxim Integrated MAX31790 I2C configurable PWM controller"
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| D | Kconfig.adp5585 | 5 bool "Analog ADP5585 I2C configurable GPIO/PWM/KeyScan chip"
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| D | Kconfig.ad559x | 5 bool "Analog AD559x I2C/SPI configurable ADC/DAC/GPIO chip"
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| /Zephyr-latest/drivers/fpga/ |
| D | Kconfig.slg471x5 | 5 bool "Renesas SLG47105/SLG47115 GreenPAK Configurable Mixed-Signal IC"
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| /Zephyr-latest/boards/efinix/titanium_ti60_f225/doc/ |
| D | index.rst | 8 which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set an…
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_dw_common.c | 23 LOG_WRN("Pausing watchdog by debugger is not configurable"); in dw_wdt_check_options()
27 LOG_WRN("Pausing watchdog in sleep is not configurable"); in dw_wdt_check_options()
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| /Zephyr-latest/doc/introduction/ |
| D | index.rst | 93 **Highly configurable / Modular for flexibility**
103 Implements configurable architecture-specific stack-overflow protection,
147 * Highly configurable
153 * Highly configurable, fitting in devices with at least 16k RAM
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| /Zephyr-latest/doc/connectivity/bluetooth/ |
| D | features.rst | 19 * Highly configurable
80 * Highly configurable, fits as small as 16k RAM devices
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| /Zephyr-latest/dts/bindings/adc/ |
| D | st,stm32-adc.yaml | 104 - "NOT_FULLY_CONFIGURABLE": Not fully configurable sequencer
105 - "FULLY_CONFIGURABLE": Fully configurable sequencer
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| /Zephyr-latest/soc/nordic/nrf91/ |
| D | Kconfig.soc | 36 # That's why in the top level of SoC definitions (for user-configurable
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| /Zephyr-latest/dts/bindings/i2s/ |
| D | nordic,nrf-i2s.yaml | 33 - "ACLK": Audio PLL clock with configurable frequency (frequency for
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| /Zephyr-latest/dts/bindings/phy/ |
| D | st,stm32u5-otghs-phy.yaml | 7 with USB HS PHY IP and a configurable HSE clock source.
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| /Zephyr-latest/dts/bindings/audio/ |
| D | nordic,nrf-pdm.yaml | 32 - "ACLK": Audio PLL clock with configurable frequency (frequency for
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| /Zephyr-latest/soc/nordic/nrf92/ |
| D | Kconfig.soc | 14 # and user-configurable Kconfigs, since that's what visible to users.
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| /Zephyr-latest/include/zephyr/arch/arm/cortex_m/ |
| D | exception.h | 26 * the highest configurable priority level (level 0); note, however, that
31 * with configurable priority.
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