| /Zephyr-latest/samples/drivers/clock_control_litex/ |
| D | README.rst | 1 .. zephyr:code-sample:: clock-control-litex
2 :name: LiteX clock control driver
3 :relevant-api: clock_control_interface
5 Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
17 * Optional: clock output signals redirected to output pins for testing
21 …tion of the driver, including default settings for clock outputs, is held in Device Tree clock con…
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | clock_control_litex.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief LiteX Clock Control driver interface
16 * @brief LiteX Clock Control driver interface
17 * @defgroup clock_control_litex_interface LiteX Clock Control driver interface
18 * @brief LiteX Clock Control driver interface
29 * @brief Structure for interfacing with clock control API
31 * @param clkout_nr Number of clock output to be changed
32 * @param rate Frequency to set given in Hz
34 * @param duty Duty cycle of clock signal in percent
39 uint32_t rate; member
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| /Zephyr-latest/dts/bindings/video/ |
| D | ovti,ov2640.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 reset-gpios:
10 type: phandle-array
13 reset. The sensor receives this as an active-low signal.
15 clock-rate-control:
19 Define the value to the Clock Rate Control register. By changing
20 the system clock divide ratio and PLL, the frame rate and pixel
21 rate will change together.
25 Bit[5:0] Clock divider.
29 include: i2c-device.yaml
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | clock_control.h | 1 /* clock_control.h - public clock controller driver API */
6 * SPDX-License-Identifier: Apache-2.0
11 * @brief Public Clock Control APIs
18 * @brief Clock Control Interface
19 * @defgroup clock_control_interface Clock Control Interface
38 /* Clock control API */
40 /* Used to select all subsystem of a clock controller */
44 * @brief Current clock status.
54 * clock_control_subsys_t is a type to identify a clock controller sub-system.
55 * Such data pointed is opaque and relevant only to the clock controller
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| /Zephyr-latest/samples/drivers/clock_control_xec/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
24 uint32_t r = pcr->PWR_RST_STS; in pcr_clock_regs()
30 r = pcr->OSC_ID; in pcr_clock_regs()
33 r = pcr->PROC_CLK_CTRL; in pcr_clock_regs()
34 LOG_INF("PCR Processor Clock Control register = 0x%x", r); in pcr_clock_regs()
36 r = pcr->SLOW_CLK_CTRL; in pcr_clock_regs()
37 LOG_INF("PCR Slow Clock Control register = 0x%x", r); in pcr_clock_regs()
43 uint32_t cken = vbr->CLK32_EN; in vbat_clock_regs()
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| /Zephyr-latest/soc/nxp/rw/ |
| D | flexspi_clock_setup.c | 2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
15 * @brief Set flexspi clock to given frequency
19 * is used by the clock control framework to set the clock frequency of
22 int __ramfunc flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) in flexspi_clock_set_freq() argument
29 /* Get the root clock rate: FlexSPI clock * divisor */ in flexspi_clock_set_freq()
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
45 set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL & in flexspi_clock_set_freq()
58 * @brief Set flexspi clock
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| /Zephyr-latest/drivers/clock_control/ |
| D | beetle_clock_control.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Driver for Clock Control of Beetle MCUs.
13 * This file contains the Clock Control driver implementation for the
26 /* Clock Control ID */
28 /* Clock control freq */
59 beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0set), in beetle_ahb_set_clock_on()
66 beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0clr), in beetle_ahb_set_clock_off()
73 beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0set), in beetle_apb_set_clock_on()
80 beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0clr), in beetle_apb_set_clock_off()
92 switch (beetle_cc->bus) { in beetle_clock_control_on()
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| D | clock_control_pwm.c | 4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/pwm/pwm.h>
23 "PWM must have a higher priority than PWM clock control");
39 struct clock_control_pwm_data *data = dev->data; in clock_control_pwm_on()
40 const struct clock_control_pwm_config *config = dev->config; in clock_control_pwm_on()
46 return -EINVAL; in clock_control_pwm_on()
49 spec = &config->pwm_dt; in clock_control_pwm_on()
50 if (data->clock_frequency == 0) { in clock_control_pwm_on()
51 ret = pwm_set_dt(spec, spec->period, spec->period / 2); in clock_control_pwm_on()
56 ret = pwm_get_cycles_per_sec(spec->dev, spec->channel, &cycles_per_sec); in clock_control_pwm_on()
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| D | clock_control_ast10x0.c | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/ast10x0_clock.h>
22 * - Each bit in these registers controls a clock gate
23 * - Write '1' to a bit: turn OFF the corresponding clock
24 * - Write '0' to a bit: no effect
26 * - Write '1' to a bit: clear the corresponding bit in CLK_STOP_CTRL0/1.
27 * (turn ON the corresponding clock)
50 #define DEV_CFG(dev) ((const struct clock_aspeed_config *const)(dev)->config)
54 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_on()
58 /* there is no on/off control for group2 clocks */ in aspeed_clock_control_on()
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| D | clock_control_lpc11u6x.h | 4 * SPDX-License-Identifier: Apache-2.0
55 volatile uint32_t p_reset_ctrl; /* Peripheral reset control */
56 volatile uint32_t sys_pll_ctrl; /* System PLL control */
58 volatile uint32_t usb_pll_ctrl; /* USB PLL control */
61 volatile uint32_t rtc_osc_ctrl; /* RTC oscillator control */
62 volatile uint32_t sys_osc_ctrl; /* System oscillator control */
64 * control
66 volatile uint32_t irc_ctrl; /* IRC Control */
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
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| D | clock_stm32_ll_wba.c | 4 * SPDX-License-Identifier: Apache-2.0
38 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) in get_bus_clock() argument
40 return clock / prescaler; in get_bus_clock()
43 /** @brief Verifies clock is part of active clock configuration */
62 return -ENOTSUP; in enabled_clock()
73 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
74 /* Attempt to toggle a wrong periph clock bit */ in stm32_clock_control_on()
75 return -ENOTSUP; in stm32_clock_control_on()
78 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_on()
79 pclken->enr); in stm32_clock_control_on()
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| D | clock_control_npcm.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
25 * Core Domain Clock Generator (CDCG) device registers
28 /* High Frequency Clock Generator (HFCG) registers */
29 /* 0x000: HFCG Control */
44 /* 0x010: HFCG Bus Clock Dividers */
47 /* 0x012: HFCG Bus Clock Dividers */
50 /* 0x014: HFCG Bus Clock Dividers */
53 /* 0x01d: HFCG Bus Clock Dividers */
57 /* clock bus references */
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| D | clock_control_numaker_scc.c | 4 * SPDX-License-Identifier: Apache-2.0
31 if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) { in numaker_scc_on()
33 CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_on()
36 return -EINVAL; in numaker_scc_on()
48 if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) { in numaker_scc_off()
50 CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx); in numaker_scc_off()
53 return -EINVAL; in numaker_scc_off()
60 uint32_t *rate) in numaker_scc_get_rate() argument
64 ARG_UNUSED(rate); in numaker_scc_get_rate()
65 return -ENOTSUP; in numaker_scc_get_rate()
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-sdram.yaml | 2 # SPDX-License-Identifier: Apache-2.0
20 pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4...>;
25 power-up-delay = <100>;
26 num-auto-refresh = <8>;
27 mode-register = <0x220>;
28 refresh-rate = <603>;
33 st,sdram-control = <STM32_FMC_SDRAM_NC_9
41 st,sdram-timing = <2 6 4 6 2 2 2>;
51 Note that you will find definitions for the st,sdram-control field at
52 dt-bindings/memory-controller/stm32-fmc-sdram.h. This file is already included
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| /Zephyr-latest/dts/bindings/serial/ |
| D | uart-controller.yaml | 8 clock-frequency:
10 description: Clock frequency information for UART operation
11 current-speed:
13 description: Initial baud rate setting for UART
14 hw-flow-control:
16 description: Set to enable RTS/CTS flow control at boot time
23 - "none"
24 - "odd"
25 - "even"
26 stop-bits:
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| D | renesas,smartbond-uart.yaml | 3 compatible: "renesas,smartbond-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
14 periph-clock-config:
16 description: Peripheral clock register configuration (COM domain)
19 current-speed:
21 Initial baud rate setting for UART. Only a fixed set of baud
24 - 4800
25 - 9600
26 - 14400
27 - 19200
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| /Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
162 uint32_t rate; in test_request_release_clock_spec() local
164 TC_PRINT("Clock under test: %s\n", clk_dev->name); in test_request_release_clock_spec()
171 } while (ret == -EAGAIN); in test_request_release_clock_spec()
172 TC_PRINT("Clock control request return value: %d\n", ret); in test_request_release_clock_spec()
173 TC_PRINT("Clock control request response code: %d\n", res); in test_request_release_clock_spec()
176 ret = clock_control_get_rate(clk_dev, NULL, &rate); in test_request_release_clock_spec()
177 if (ret != -ENOSYS) { in test_request_release_clock_spec()
179 zassert_equal(rate, clk_spec->frequency); in test_request_release_clock_spec()
196 clk_specs_size = clk_context->clk_specs_size; in test_clock_control_request()
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| /Zephyr-latest/samples/drivers/clock_control_litex/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
13 /* Select clock outputs for tests [0-6] */
62 /* LiteX Common Clock Driver tests */
66 uint32_t rate; in litex_clk_test_getters() local
75 printf("CLKOUT%d: get_status: rate:%d phase:%d duty:%d\n", in litex_clk_test_getters()
76 i, setup.rate, setup.phase, setup.duty); in litex_clk_test_getters()
77 clock_control_get_rate(dev, sub_system, &rate); in litex_clk_test_getters()
78 printf("CLKOUT%d: get_rate:%d\n", i, rate); in litex_clk_test_getters()
88 .rate = LITEX_TEST_SINGLE_FREQ_VAL, in litex_clk_test_single()
94 .rate = LITEX_TEST_SINGLE_FREQ_VAL2, in litex_clk_test_single()
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| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_dw1000_regs.h | 4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
110 /* Disable Smart TX Power control */
112 /* Receiver Mode 110 kbps data rate */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
123 /* Automatic Acknowledgement Pending bit control */
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| /Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/ |
| D | mini_stm32h743.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 /* AHB clocks must respect the minimum ratio AHB / DCMI_PIXCLK of 2.5 (AN5020 - Rev 3).
13 clock-frequency = <DT_FREQ_M(240)>;
23 * 100: HSI48 clock selected (hsi48_ck)
36 pinctrl-0 = <&rcc_mco_1_pa8>;
37 pinctrl-names = "default";
42 supply-gpios = <&dcmi_camera_connector 8 GPIO_ACTIVE_HIGH>;
43 clock-rate-control = <0x80>;
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | nxp,mcux-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-qdec"
8 include: [pinctrl-device.yaml, sensor-device.yaml]
17 counts-per-revolution:
24 single-phase-mode:
28 generates a count signal. The PHASEB input and the REV bit control the
31 filter-count:
39 filter-sample-period:
42 The sampling period (in IPBus clock cycles) of the decoder input signals.
43 Each input is sampled multiple times at the rate specified by the Filter
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_uart.h | 4 * SPDX-License-Identifier: Apache-2.0
24 * LCR DLAB=1, BAUD rate divisor LSB
32 * LCR DLAB=1, BAUD rate divisor MSB
43 /* FIFO Control Register, Write-Only */
47 #define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */
48 #define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
56 /* Interrupt Identification Register, Read-Only */
67 * Highest-1. RX data available or RX FIFO trigger level reached
68 * Highest-2. RX timeout
69 * Highest-3. TX Holding register empty
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| /Zephyr-latest/boards/seeed/xiao_esp32s3/ |
| D | xiao_esp32s3_procpu_sense.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "seeed,xiao-esp32s3";
22 clock-frequency = <I2C_BITRATE_STANDARD>;
23 pinctrl-0 = <&i2c1_default>;
24 pinctrl-names = "default";
30 clock-rate-control = <0x80>;
33 remote-endpoint-label = "dvp_ep_in";
45 cam-clk = <10000000>;
46 pinctrl-0 = <&lcd_cam_default>;
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| /Zephyr-latest/drivers/serial/ |
| D | uart_pl011_registers.h | 6 * SPDX-License-Identifier: Apache-2.0
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
58 /* PL011 Integer baud rate register */
61 /* PL011 Fractional baud rate register */
74 /* PL011 Line Control Register */
84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5)
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| /Zephyr-latest/include/zephyr/lorawan/ |
| D | lorawan.h | 4 * SPDX-License-Identifier: Apache-2.0
40 LORAWAN_ACT_OTAA = 0, /**< Over-the-Air Activation (OTAA) */
64 LORAWAN_DR_0 = 0, /**< DR0 data rate */
65 LORAWAN_DR_1, /**< DR1 data rate */
66 LORAWAN_DR_2, /**< DR2 data rate */
67 LORAWAN_DR_3, /**< DR3 data rate */
68 LORAWAN_DR_4, /**< DR4 data rate */
69 LORAWAN_DR_5, /**< DR5 data rate */
70 LORAWAN_DR_6, /**< DR6 data rate */
71 LORAWAN_DR_7, /**< DR7 data rate */
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