4  * SPDX-License-Identifier: Apache-2.0
11  * @brief Driver for Clock Control of Beetle MCUs.
13  * This file contains the Clock Control driver implementation for the
26 	/* Clock Control ID */
28 	/* Clock control freq */
59 	beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0set),  in beetle_ahb_set_clock_on()
66 	beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->ahbclkcfg0clr),  in beetle_ahb_set_clock_off()
73 	beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0set),  in beetle_apb_set_clock_on()
80 	beetle_set_clock((volatile uint32_t *)&(__BEETLE_SYSCON->apbclkcfg0clr),  in beetle_apb_set_clock_off()
92 	switch (beetle_cc->bus) {  in beetle_clock_control_on()
94 		bit = (beetle_cc->device - _BEETLE_AHB_BASE) >> 12;  in beetle_clock_control_on()
95 		beetle_ahb_set_clock_on(bit, beetle_cc->state);  in beetle_clock_control_on()
98 		bit = (beetle_cc->device - _BEETLE_APB_BASE) >> 12;  in beetle_clock_control_on()
99 		beetle_apb_set_clock_on(bit, beetle_cc->state);  in beetle_clock_control_on()
116 	switch (beetle_cc->bus) {  in beetle_clock_control_off()
118 		bit = (beetle_cc->device - _BEETLE_AHB_BASE) >> 12;  in beetle_clock_control_off()
119 		beetle_ahb_set_clock_off(bit, beetle_cc->state);  in beetle_clock_control_off()
122 		bit = (beetle_cc->device - _BEETLE_APB_BASE) >> 12;  in beetle_clock_control_off()
123 		beetle_apb_set_clock_off(bit, beetle_cc->state);  in beetle_clock_control_off()
131 static int beetle_clock_control_get_subsys_rate(const struct device *clock,  in beetle_clock_control_get_subsys_rate()  argument
133 						uint32_t *rate)  in beetle_clock_control_get_subsys_rate()  argument
137 						clock->config;  in beetle_clock_control_get_subsys_rate()
138 	uint32_t nc_mainclk = beetle_round_freq(cfg->freq);  in beetle_clock_control_get_subsys_rate()
140 	*rate = nc_mainclk;  in beetle_clock_control_get_subsys_rate()
142 	ARG_UNUSED(clock);  in beetle_clock_control_get_subsys_rate()
145 	*rate = MAINCLK_BASE_FREQ;  in beetle_clock_control_get_subsys_rate()
206 	__BEETLE_SYSCON->pllctrl = BEETLE_PLL_CONFIGURATION;  in beetle_pll_enable()
208 	/* Switch the Main clock to PLL and set prescaler */  in beetle_pll_enable()
209 	__BEETLE_SYSCON->mainclk = pre_mainclk;  in beetle_pll_enable()
211 	while (!__BEETLE_SYSCON->pllstatus) {  in beetle_pll_enable()
223 						dev->config;  in beetle_clock_control_init()
229 	if (cfg->freq != MAINCLK_BASE_FREQ) {  in beetle_clock_control_init()
230 		beetle_pll_enable(cfg->freq);  in beetle_clock_control_init()
243  * @brief Clock Control device init