Lines Matching +full:clock +full:- +full:rate +full:- +full:control

1 .. zephyr:code-sample:: clock-control-litex
2    :name: LiteX clock control driver
3    :relevant-api: clock_control_interface
5    Use LiteX clock control driver to generate multiple clock signals.
10 This sample is providing an overview of LiteX clock control driver capabilities.
11 The driver uses Mixed Mode Clock Manager (MMCM) module to generate up to 7 clocks with defined phas…
15 * LiteX-capable FPGA platform with MMCM modules (for example Digilent Arty A7 development board)
16 * SoC configuration with VexRiscv soft CPU and Xilinx 7-series MMCM interface in LiteX (S7MMCM modu…
17 * Optional: clock output signals redirected to output pins for testing
21 …tion of the driver, including default settings for clock outputs, is held in Device Tree clock con…
23 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
25    :start-at: clk0: clock-controller@0 {
26    :end-at: };
29 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
31    :start-at: clk1: clock-controller@1 {
32    :end-at: };
35 .. literalinclude:: ../../../dts/riscv/riscv32-litex-vexriscv.dtsi
37    :start-at: clock0: clock@e0004800 {
38    :end-at: };
41 …clock outputs: ``clk0`` and ``clk1`` with default frequency set to 100MHz, 0 degrees phase offset …
43 **Important note:**  ``reg`` properties in ``clk0`` and ``clk1`` nodes reference the clock output n…
48 The driver is interfaced with the :ref:`Clock Control API <clock_control_api>` function ``clock_con…
50 | To change clock parameter it is needed to cast a pointer to structure :c:struct:`litex_clk_setup`…
53 .. code-block:: c
59 		.rate = 50000000,
70 Clock output status (frequency, duty and phase offset) can be acquired with function ``clock_contro…
72 …rol_on()``. Structure ``litex_clk_setup`` is used to set ``clkout_nr`` of clock output from which …
77 This example provides a simple way of checking various clock output settings. User can pick one of …
82 * Setting frequency, duty and phase at once, then check clock status and rate,
91 Code is performed on 2 clock outputs with ``clkout_nr`` defined in ``LITEX_CLK_TEST_CLK1`` and ``LI…
96 .. code-block:: none
98   west build -b litex_vexriscv zephyr/samples/drivers/clock_control
105 .. code-block:: none
107   [00:00:00.200,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set rate: 100000000 HZ
108   [00:00:00.240,000] <inf> CLK_CTRL_LITEX: CLKOUT1: updated rate: 100000000 to 100000000 HZ
111   [00:00:00.360,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set rate: 100000000 HZ
114   [00:00:00.440,000] <inf> CLK_CTRL_LITEX: LiteX Clock Control driver initialized
115   *** Booting Zephyr OS build zephyr-v2.2.0-2810-g1ca5dda196c3  ***
116   Clock Control Example! riscv32
118   clock control device is 0x40013460, name is clock0
119   Clock test
121   [00:00:00.510,000] <inf> CLK_CTRL_LITEX: CLKOUT0: set rate: 15000000 HZ
124   [00:00:00.630,000] <inf> CLK_CTRL_LITEX: CLKOUT1: set rate: 15000000 HZ
127   CLKOUT0: get_status: rate:15000000 phase:90 duty:25
129   CLKOUT1: get_status: rate:15000000 phase:0 duty:75
131   Clock test done returning: 0
136 - :zephyr:board:`litex_vexriscv`