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/Zephyr-Core-2.7.6/dts/arm/atmel/
Dsamd20.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-0 = &tc0;
12 tc-2 = &tc2;
13 tc-6 = &tc6;
18 compatible = "atmel,sam0-tc32";
23 clock-names = "GCLK", "PM";
27 compatible = "atmel,sam0-tc32";
32 clock-names = "GCLK", "PM";
36 compatible = "atmel,sam0-tc32";
41 clock-names = "GCLK", "PM";
[all …]
Dsamd21.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 tc-6 = &tc6;
16 compatible = "atmel,sam0-usb";
20 num-bidir-endpoints = <8>;
25 compatible = "atmel,sam0-dmac";
29 #dma-cells = <2>;
33 compatible = "atmel,sam0-tc32";
38 clock-names = "GCLK", "PM";
42 compatible = "atmel,sam0-tcc";
47 clock-names = "GCLK", "PM";
[all …]
Dsamr21.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include "samr2x-pinctrl.dtsi"
13 port-c = &portc;
18 compatible = "atmel,sam0-usb";
22 num-bidir-endpoints = <8>;
27 compatible = "atmel,sam0-dmac";
31 #dma-cells = <2>;
38 compatible = "atmel,sam0-gpio";
41 gpio-controller;
42 #gpio-cells = <2>;
[all …]
Dsamd5x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
11 #include "samd5x-pinctrl.dtsi"
15 zephyr,flash-controller = &nvmctrl;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
26 #address-cells = <1>;
[all …]
/Zephyr-Core-2.7.6/dts/riscv/
Driscv32-litex-vexriscv.dtsi2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "litex,vexriscv", "litex-dev";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 clock-frequency = <100000000>;
28 timebase-frequency = <32768>;
32 #address-cells = <1>;
[all …]
/Zephyr-Core-2.7.6/dts/bindings/base/
Dbase.yaml11 - "ok" # Deprecated form
12 - "okay"
13 - "disabled"
14 - "reserved"
15 - "fail"
16 - "fail-sss"
19 type: string-array
28 reg-names:
29 type: string-array
38 # Does not follow the 'type: phandle-array' scheme, but gets type-checked
[all …]
/Zephyr-Core-2.7.6/dts/riscv/starfive/
Dstarfive_jh7100_beagle_v.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 timebase-frequency = <6250000>;
20 compatible = "starfive,fu74-g000";
[all …]
/Zephyr-Core-2.7.6/include/devicetree/
Dclocks.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-clocks Devicetree Clocks API
27 * "clocks" phandle-array property at an index
31 * clk1: clock-controller@... { ... };
33 * clk2: clock-controller@... { ... };
46 * @return the node identifier for the clock controller referenced at
64 * clocks phandle-array property at an index
69 * clk1: clock-controller@... { ... };
71 * clk2: clock-controller@... { ... };
75 * clock-names = "alpha", "beta";
[all …]
/Zephyr-Core-2.7.6/dts/bindings/clock/
Dnxp,lpc11u6x-syscon.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: LPC11U6X clock controller node
6 compatible: "nxp,lpc11u6x-syscon"
8 include: [clock-controller.yaml, base.yaml]
18 type: phandle-array
22 pinmux-names:
23 type: string-array
25 description: system oscillator pins names
27 "#clock-cells":
30 clock-cells:
[all …]
Dlitex,clk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
[all …]
/Zephyr-Core-2.7.6/dts/arm/nxp/
Dnxp_k6x.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <arm/armv7-m.dtsi>
5 #include <dt-bindings/clock/kinetis_sim.h>
6 #include <dt-bindings/clock/kinetis_mcg.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/i2c/i2c.h>
17 zephyr,flash-controller = &ftfe;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-m4f";
[all …]
Dnxp_kv5x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/clock/kinetis_sim.h>
9 #include <dt-bindings/clock/kinetis_mcg.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/i2c/i2c.h>
15 zephyr,flash-controller = &ftfe;
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-m7";
[all …]
Dnxp_ke1xf.dtsi2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/clock/kinetis_pcc.h>
9 #include <dt-bindings/clock/kinetis_scg.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/i2c/i2c.h>
19 zephyr,flash-controller = &ftfe;
23 #address-cells = <1>;
24 #size-cells = <0>;
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/f0/
Dstm32f0.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv6-m.dtsi>
9 #include <dt-bindings/clock/stm32_clock.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h>
17 zephyr,flash-controller = &flash;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-m0";
[all …]
/Zephyr-Core-2.7.6/boards/arm/mps3_an547/
Dmps3_an547-common.dtsi2 * Copyright (c) 2019-2021 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
14 compatible = "arm,cmsdk-gpio";
17 gpio-controller;
18 #gpio-cells = <2>;
23 compatible = "arm,cmsdk-gpio";
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/f4/
Dstm32f4.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <dt-bindings/clock/stm32_clock.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h>
17 zephyr,flash-controller = &flash;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-Core-2.7.6/tests/lib/devicetree/api/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * Names in this file should be chosen in a way that won't conflict
9 * with real-world devicetree nodes, to allow these tests to run on
15 test-alias = &test_nodelabel;
23 #address-cells = < 0x1 >;
24 #size-cells = < 0x1 >;
25 interrupt-parent = <&test_intc>;
27 test_pinctrl: pin-controller {
29 test_pincfg_a: pincfg-a {};
30 test_pincfg_b: pincfg-b {};
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/f3/
Dstm32f3.dtsi2 * Copyright (c) 2017 I-SENSE group of ICCS
5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <dt-bindings/clock/stm32_clock.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h>
17 zephyr,flash-controller = &flash;
21 #address-cells = <1>;
22 #size-cells = <0>;
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/g0/
Dstm32g0.dtsi6 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
8 * SPDX-License-Identifier: Apache-2.0
11 #include <arm/armv6-m.dtsi>
12 #include <dt-bindings/clock/stm32_clock.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/i2c/i2c.h>
15 #include <dt-bindings/pwm/pwm.h>
20 zephyr,flash-controller = &flash;
24 #address-cells = <1>;
25 #size-cells = <0>;
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/f7/
Dstm32f7.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <dt-bindings/clock/stm32_clock.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h>
18 zephyr,flash-controller = &flash;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m7";
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/g4/
Dstm32g4.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <dt-bindings/clock/stm32_clock.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pwm/pwm.h>
18 zephyr,flash-controller = &flash;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-m4f";
[all …]
/Zephyr-Core-2.7.6/boards/arm/mps2_an521/
Dmps2_an521-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
14 compatible = "arm,cmsdk-timer";
21 compatible = "arm,cmsdk-timer";
28 compatible = "arm,cmsdk-dtimer";
49 compatible = "arm,cmsdk-gpio";
52 gpio-controller;
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/f1/
Dstm32f105.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 /delete-node/ pll;
14 #clock-cells = <0>;
15 compatible = "st,stm32f105-pll-clock";
20 #clock-cells = <0>;
21 compatible = "st,stm32f105-pll2-clock";
28 flash-controller@40022000 {
30 erase-block-size = <DT_SIZE_K(2)>;
35 compatible = "st,stm32-can";
36 #address-cells = <1>;
[all …]
/Zephyr-Core-2.7.6/dts/arc/
Darc_iot.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
23 intc: arcv2-intc {
24 compatible = "snps,arcv2-intc";
25 interrupt-controller;
26 #interrupt-cells = <2>;
42 compatible = "mmio-sram";
[all …]
/Zephyr-Core-2.7.6/dts/arm/st/wl/
Dstm32wl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/clock/stm32_clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <dt-bindings/lora/sx126x.h>
12 #include <dt-bindings/pwm/pwm.h>
18 zephyr,flash-controller = &flash;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]

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