Lines Matching +full:clock +full:- +full:names
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
10 compatible = "litex,vexriscv", "litex-dev";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 clock-frequency = <100000000>;
28 timebase-frequency = <32768>;
32 #address-cells = <1>;
33 #size-cells = <1>;
36 intc0: interrupt-controller@bc0 {
37 #interrupt-cells = <2>;
38 compatible = "vexriscv-intc0";
39 interrupt-controller;
41 reg-names = "irq_mask", "irq_pending";
42 riscv,max-priority = <7>;
46 interrupt-parent = <&intc0>;
49 reg-names = "control";
55 interrupt-parent = <&intc0>;
58 reg-names = "control";
61 #address-cells = <1>;
62 #size-cells = <0>;
66 interrupt-parent = <&intc0>;
69 reg-names = "control";
75 interrupt-parent = <&intc0>;
78 local-mac-address = [10 e2 d5 00 00 02];
79 reg-names = "control", "buffers";
85 /* DNA data is 57-bits long,
87 In LiteX each 32-bit register holds
91 reg-names = "mem";
98 reg-names = "write", "read";
100 #address-cells = <1>;
101 #size-cells = <0>;
107 reg-names = "control";
110 port-is-output;
112 gpio-controller;
113 #gpio-cells = <2>;
122 interrupt-parent = <&intc0>;
124 reg-names = "base",
132 gpio-controller;
133 #gpio-cells = <2>;
138 reg-names = "status";
145 reg-names = "enable", "width", "period";
148 #pwm-cells = <2>;
153 interrupt-parent = <&intc0>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 reg-names = "control", "fifo";
165 interrupt-parent = <&intc0>;
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg-names = "control", "fifo";
174 clock-outputs {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 clk0: clock-controller@0 {
178 #clock-cells = <1>;
181 clock-output-names = "CLK_0";
182 litex,clock-frequency = <100000000>;
183 litex,clock-phase = <0>;
184 litex,clock-duty-num = <1>;
185 litex,clock-duty-den = <2>;
186 litex,clock-margin = <1>;
187 litex,clock-margin-exp = <2>;
190 clk1: clock-controller@1 {
191 #clock-cells = <1>;
194 clock-output-names = "CLK_1";
195 litex,clock-frequency = <100000000>;
196 litex,clock-phase = <0>;
197 litex,clock-duty-num = <1>;
198 litex,clock-duty-den = <2>;
199 litex,clock-margin = <1>;
200 litex,clock-margin-exp = <2>;
204 clock0: clock@82005000 {
215 reg-names = "drp_reset",
223 #clock-cells = <1>;
225 clock-output-names = "CLK_0", "CLK_1";
226 litex,lock-timeout = <10>;
227 litex,drdy-timeout = <10>;
228 litex,sys-clock-frequency = <100000000>;
229 litex,divclk-divide-min = <1>;
230 litex,divclk-divide-max = <107>;
231 litex,clkfbout-mult-min = <2>;
232 litex,clkfbout-mult-max = <65>;
233 litex,vco-freq-min = <600000000>;
234 litex,vco-freq-max = <1200000000>;
235 litex,clkout-divide-min = <1>;
236 litex,clkout-divide-max = <126>;
237 litex,vco-margin = <0>;