Searched +full:clock +full:- +full:margin +full:- +full:exp (Results 1 – 4 of 4) sorted by relevance
2 # SPDX-License-Identifier: Apache-2.07 LiteX Mixed Mode Clock Manager clock output binding13 "#clock-cells":17 Number of cells in a clock specifier;18 Typically 0 for nodes with a single clock output19 and 1 for nodes with multiple clock outputs.22 clock-output-names:26 string of clock output signal name.28 litex,clock-frequency:32 default frequency in Hz for clock output[all …]
2 * Copyright (c) 2018 - 2020 Antmicro <www.antmicro.com>4 * SPDX-License-Identifier: Apache-2.08 #address-cells = <1>;9 #size-cells = <1>;10 compatible = "litex,vexriscv", "litex-dev";19 #address-cells = <1>;20 #size-cells = <0>;22 clock-frequency = <100000000>;28 timebase-frequency = <32768>;32 #address-cells = <1>;[all …]
4 * SPDX-License-Identifier: Apache-2.065 lcko = &ldev->clkouts[N]; \66 lcko->id = CLKOUT_ID(N); \68 lcko->clkout_div = clkout_div; \69 lcko->def.freq = CLKOUT_FREQ(N); \70 lcko->def.phase = CLKOUT_PHASE(N); \71 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \72 lcko->def.duty.den = CLKOUT_DUTY_DEN(N); \73 lcko->margin.m = CLKOUT_MARGIN(N); \74 lcko->margin.exp = CLKOUT_MARGIN_EXP(N);[all …]
4 * SPDX-License-Identifier: Apache-2.064 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…211 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()217 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()232 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()249 timeout = ldev->timeout.lock; in litex_clk_wait()251 timeout = ldev->timeout.drdy; in litex_clk_wait()255 timeout--; in litex_clk_wait()260 return -ETIME; in litex_clk_wait()301 ldev->g_config.mul = 1; in litex_clk_update_global_config()[all …]
