Searched +full:clock +full:- +full:frequency (Results 1 – 25 of 1024) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/timer/ |
| D | andestech,atcpit100.yaml | 4 # SPDX-License-Identifier: Apache-2.0
21 clock-frequency:
24 description: channel clock source
30 The prescaler value defines the counter frequency
31 (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler
32 value could be in range [1 .. clock-frequency] and 1 means no prescaler
33 for the PIT clock-frequency.
35 Defaults to 1 to use the PIT clock-frequency as the counter frequency.
38 larger than a counter tick period, reducing the counter frequency to
42 clock cycles for counter interface, setting prescaler value to 600 in
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| D | nuclei,systimer.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
24 clk-divider specifies the division ratio to the CPU frequency that
25 clock used by the system timer.
27 different clock sources.
30 For example, the CPU clock frequency is 108MHz, and the system timer
31 uses 27MHz, which is the CPU clock divided by 4.
32 In this case, the CPU clock frequency is defined in the CPU node
35 clock-frequency = <108000000>;
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | st,stm32wba-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
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| D | st,stm32h7-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
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| D | st,stm32l0-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
8 input frequency from 2 to 24 MHz.
10 The desired PLL frequency can be computed with the following formula:
12 f(PLL) = f(VCO clock) / PLLDIV --> PLLCLK (System Clock)
14 with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16 The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
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| D | litex,clk.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 include: [clock-controller.yaml, base.yaml]
7 LiteX Mixed Mode Clock Manager
8 Common clock driver with MMCM unit for dynamic reconfiguration
9 of up to 7 clock outputs with ability to change frequency, duty
14 clock-cells:
15 - id
22 "#clock-cells":
26 clock-output-names:
28 type: string-array
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| D | st,stm32-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
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| D | st,stm32wba-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 This PLL could take one of clk_hse or clk_hsi as input clock, with
10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11 clock in this acceptable range.
13 PLL1 can have up to 3 output clocks and for each output clock, the
14 frequency can be computed with the following formula:
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32u5-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 These PLLs could take one of clk_hse, clk_hsi or clk_msis as input clock, with
10 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11 clock in this acceptable range.
13 Each PLL can have up to 3 output clocks and for each output clock, the
14 frequency can be computed with the following formulae:
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | nordic,nrf-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF clock control node
6 compatible: "nordic,nrf-clock"
17 hfclkaudio-frequency:
20 Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm
21 resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and
23 The HFCLKAUDIO clock is only available in the nRF53 Series SoCs.
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| D | st,stm32g4-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 It can take one of clk_hse or clk_hsi as input clock, with
8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
12 frequency can be computed with the following formulae:
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48MCLK (for USB, RNG)
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f4-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 Takes one of clk_hse or clk_hsi as input clock, with an
8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
11 Up to 2 output clocks could be supported and for each output clock, the
12 frequency can be computed with the following formula:
14 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
19 The PLL output frequency must not exceed 80 MHz.
22 compatible: "st,stm32f4-pll-clock"
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| D | st,stm32g0-pll-clock.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 It can take one of clk_hse or clk_hsi as input clock, with
8 an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
12 frequency can be computed with the following formulae:
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| /Zephyr-Core-3.5.0/dts/riscv/starfive/ |
| D | starfive_jh7100_clk.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | adsp_clk.h | 4 * SPDX-License-Identifier: Apache-2.0
20 /** @brief Set cAVS clock frequency
22 * Set xtensa core clock speed.
24 * @param freq Clock frequency index to be set
26 * @return 0 on success, -EINVAL if freq_idx is not valid
30 /** @brief Get list of cAVS clock information
32 * Returns an array of clock information, one for each core.
34 * @return array with clock information
65 /* Clock sources used by dai */
81 uint32_t frequency; member
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| /Zephyr-Core-3.5.0/soc/arm/silabs_exx32/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
49 Set if the Back-Up Real Time Counter (BURTC) HAL module is used.
85 Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used.
216 Set if the clock management unit (CMU) is present in the SoC.
224 in on-demand mode, after SoC is initialized.
227 prompt "High Frequency Clock Selection"
231 bool "External high frequency crystal oscillator"
233 Set this option to use the external high frequency crystal oscillator
234 as high frequency clock.
237 bool "External low frequency crystal oscillator"
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| /Zephyr-Core-3.5.0/subsys/logging/backends/ |
| D | Kconfig.swo | 2 # SPDX-License-Identifier: Apache-2.0
14 int "SWO reference clock frequency"
15 …default $(dt_node_int_prop_int,$(dt_nodelabel_path,itm),swo-ref-frequency) if $(dt_nodelabel_enabl…
16 …default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if $(dt_node_has_prop,/cpus/cpu@0,cloc…
19 Set SWO reference frequency. In most cases it is equal to CPU
20 frequency.
23 int "Set SWO output frequency"
26 Set SWO output frequency. Value 0 will select maximum frequency
28 frequency SWO operation. In this case the frequency has to be set
32 viewer programs will configure SWO frequency when attached to the
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| /Zephyr-Core-3.5.0/dts/bindings/rtc/ |
| D | rtc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 clock-frequency:
11 description: Clock frequency information for RTC operation
17 description: RTC frequency equals clock-frequency divided by the prescaler value
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| /Zephyr-Core-3.5.0/dts/bindings/i2s/ |
| D | nordic,nrf-i2s.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic I2S (Inter-IC sound interface)
6 compatible: "nordic,nrf-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 clock-source:
24 Clock source to be used by the I2S peripheral for the master clock
27 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
28 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
29 (HFXO) for better clock accuracy and jitter performance
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| /Zephyr-Core-3.5.0/dts/bindings/watchdog/ |
| D | snps,designware-watchdog.yaml | 3 compatible: "snps,designware-watchdog"
15 clock-frequency:
18 Clock frequency used by counter in Hz. You can specify a frequency here or specify a clock
21 reset-pulse-length:
24 - 2
25 - 4
26 - 8
27 - 16
28 - 32
29 - 64
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| D | intel,adsp-watchdog.yaml | 3 compatible: "intel,adsp-watchdog"
15 clock-frequency:
18 Clock frequency used by counter in Hz. You can specify a frequency here or specify a clock
21 reset-pulse-length:
24 - 2
25 - 4
26 - 8
27 - 16
28 - 32
29 - 64
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| /Zephyr-Core-3.5.0/dts/bindings/audio/ |
| D | nordic,nrf-pdm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-pdm"
8 include: [base.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 clock-source:
24 Clock source to be used by the PDM peripheral. The following options
26 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
27 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
28 (HFXO) for better clock accuracy and jitter performance
29 - "ACLK": Audio PLL clock with configurable frequency (frequency for
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| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | clock_control_agilex5_ll.c | 2 * Copyright (c) 2022-2023, Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
15 /* Clock manager individual group base addresses. */
23 /* Clock manager low layer(ll) params object. */
26 /* Initialize the clock ll with the given base address */
29 /* Clock manager module base address. */ in clock_agilex5_ll_init()
32 /* Clock manager main PLL base address. */ in clock_agilex5_ll_init()
35 /* Clock manager peripheral PLL base address. */ in clock_agilex5_ll_init()
38 /* Clock manager control module base address. */ in clock_agilex5_ll_init()
42 /* Extract reference clock from platform clock source */
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| /Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f0_i2c1_hsi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
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| D | f3_i2c1_hsi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
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