Lines Matching +full:clock +full:- +full:frequency

2 # SPDX-License-Identifier: Apache-2.0
7   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
8   input frequency from 2 to 24 MHz.
10   The desired PLL frequency can be computed with the following formula:
12     f(PLL) = f(VCO clock) / PLLDIV  --> PLLCLK (System Clock)
14       with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
16   The PLL output frequency must not exceed 32 MHz.
18 compatible: "st,stm32l0-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23   "#clock-cells":
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44         The PLL VCO clock frequency must not exceed:
45         - 96 MHz when the product is in Range 1
46         - 48 MHz when the product is in Range 2
47         - 24 MHz when the product is in Range 3
48         If the USB uses the PLL as clock source, the PLL VCO clock must be
49         programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
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