1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32L0 and STM32L1 Main PLL node binding:
6
7  Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
8  input frequency from 2 to 24 MHz.
9
10  The desired PLL frequency can be computed with the following formula:
11
12    f(PLL) = f(VCO clock) / PLLDIV  --> PLLCLK (System Clock)
13
14      with f(VCO clock) = f(PLL clock input) × PLLMUL --> PLLVCO
15
16  The PLL output frequency must not exceed 32 MHz.
17
18compatible: "st,stm32l0-pll-clock"
19
20include: [clock-controller.yaml, base.yaml]
21
22properties:
23  "#clock-cells":
24    const: 0
25
26  clocks:
27    required: true
28
29  div:
30    type: int
31    required: true
32    description: |
33        PLL output division
34    enum:
35      - 2
36      - 3
37      - 4
38
39  mul:
40    type: int
41    required: true
42    description: |
43        PLL multiplication factor for VCO
44        The PLL VCO clock frequency must not exceed:
45        - 96 MHz when the product is in Range 1
46        - 48 MHz when the product is in Range 2
47        - 24 MHz when the product is in Range 3
48        If the USB uses the PLL as clock source, the PLL VCO clock must be
49        programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
50    enum:
51      - 3
52      - 4
53      - 6
54      - 8
55      - 12
56      - 16
57      - 24
58      - 32
59      - 48
60