| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.rv32m1 | 1 # RV32M1 INTMUX config
4 # SPDX-License-Identifier: Apache-2.0
6 config RV32M1_INTMUX
15 eight channels; each channel has its own level 1 interrupt to
20 config RV32M1_INTMUX_INIT_PRIORITY
27 config RV32M1_INTMUX_CHANNEL_0
28 bool "INTMUX channel 0"
30 Enable support for INTMUX channel 0.
32 config RV32M1_INTMUX_CHANNEL_1
33 bool "INTMUX channel 1"
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_rv32m1_tpm.c | 7 * SPDX-License-Identifier: Apache-2.0
24 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
40 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
43 static int rv32m1_tpm_set_cycles(const struct device *dev, uint32_t channel, in rv32m1_tpm_set_cycles() argument
47 const struct rv32m1_tpm_config *config = dev->config; in rv32m1_tpm_set_cycles() local
48 struct rv32m1_tpm_data *data = dev->data; in rv32m1_tpm_set_cycles()
52 LOG_ERR("Channel can not be set to inactive level"); in rv32m1_tpm_set_cycles()
53 return -ENOTSUP; in rv32m1_tpm_set_cycles()
56 if (channel >= config->channel_count) { in rv32m1_tpm_set_cycles()
57 LOG_ERR("Invalid channel"); in rv32m1_tpm_set_cycles()
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| D | pwm_mcux_tpm.c | 8 * SPDX-License-Identifier: Apache-2.0
26 #define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
28 #define MAX_CHANNELS ARRAY_SIZE(TPM1->CONTROLS)
45 tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS]; member
48 static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel, in mcux_tpm_set_cycles() argument
52 const struct mcux_tpm_config *config = dev->config; in mcux_tpm_set_cycles() local
53 struct mcux_tpm_data *data = dev->data; in mcux_tpm_set_cycles()
57 LOG_ERR("Channel can not be set to inactive level"); in mcux_tpm_set_cycles()
58 return -ENOTSUP; in mcux_tpm_set_cycles()
61 if (channel >= config->channel_count) { in mcux_tpm_set_cycles()
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| D | pwm_mcux.c | 4 * SPDX-License-Identifier: Apache-2.0
38 pwm_signal_param_t channel[CHANNEL_COUNT]; member
42 static int mcux_pwm_set_cycles_internal(const struct device *dev, uint32_t channel, in mcux_pwm_set_cycles_internal() argument
46 const struct pwm_mcux_config *config = dev->config; in mcux_pwm_set_cycles_internal() local
47 struct pwm_mcux_data *data = dev->data; in mcux_pwm_set_cycles_internal()
56 if (period_cycles != data->period_cycles[channel] in mcux_pwm_set_cycles_internal()
57 || level != data->channel[channel].level) { in mcux_pwm_set_cycles_internal()
61 data->period_cycles[channel] = period_cycles; in mcux_pwm_set_cycles_internal()
63 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_set_cycles_internal()
65 return -EINVAL; in mcux_pwm_set_cycles_internal()
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| D | pwm_mcux_qtmr.c | 4 * SPDX-License-Identifier: Apache-2.0
35 static int mcux_qtmr_pwm_set_cycles(const struct device *dev, uint32_t channel, in mcux_qtmr_pwm_set_cycles() argument
39 const struct pwm_mcux_qtmr_config *config = dev->config; in mcux_qtmr_pwm_set_cycles() local
40 struct pwm_mcux_qtmr_data *data = dev->data; in mcux_qtmr_pwm_set_cycles()
44 if (channel >= CHANNEL_COUNT) { in mcux_qtmr_pwm_set_cycles()
45 LOG_ERR("Invalid channel"); in mcux_qtmr_pwm_set_cycles()
46 return -EINVAL; in mcux_qtmr_pwm_set_cycles()
52 lowCount = period_cycles - pulse_cycles; in mcux_qtmr_pwm_set_cycles()
55 highCount -= 1U; in mcux_qtmr_pwm_set_cycles()
58 lowCount -= 1U; in mcux_qtmr_pwm_set_cycles()
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| D | pwm_mcux_sctimer.c | 4 * SPDX-License-Identifier: Apache-2.0
36 sctimer_pwm_signal_param_t channel[CHANNEL_COUNT]; member
41 /* Helper to setup channel that has not previously been configured for PWM */
43 uint32_t channel, uint32_t period_cycles, in mcux_sctimer_new_channel() argument
46 const struct pwm_mcux_sctimer_config *config = dev->config; in mcux_sctimer_new_channel() local
47 struct pwm_mcux_sctimer_data *data = dev->data; in mcux_sctimer_new_channel()
51 data->match_period = period_cycles; in mcux_sctimer_new_channel()
53 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_sctimer_new_channel()
55 return -EINVAL; in mcux_sctimer_new_channel()
58 pwm_freq = (clock_freq / config->prescale) / period_cycles; in mcux_sctimer_new_channel()
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| D | pwm_mc_esp32.c | 4 * SPDX-License-Identifier: Apache-2.0
103 struct mcpwm_esp32_channel_config *channel) in mcpwm_esp32_duty_set() argument
105 struct mcpwm_esp32_config *config = (struct mcpwm_esp32_config *)dev->config; in mcpwm_esp32_duty_set() local
106 struct mcpwm_esp32_data *data = (struct mcpwm_esp32_data *const)(dev)->data; in mcpwm_esp32_duty_set()
110 if (channel->inverted) { in mcpwm_esp32_duty_set()
111 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
112 MCPWM_HAL_GENERATOR_MODE_FORCE_HIGH : channel->duty == 100 ? in mcpwm_esp32_duty_set()
115 duty_type = channel->duty == 0 ? in mcpwm_esp32_duty_set()
116 MCPWM_HAL_GENERATOR_MODE_FORCE_LOW : channel->duty == 100 ? in mcpwm_esp32_duty_set()
120 uint32_t timer_clk_hz = data->mcpwm_clk_hz / config->prescale / channel->prescale; in mcpwm_esp32_duty_set()
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| D | pwm_nxp_s32_emios.c | 4 * SPDX-License-Identifier: Apache-2.0
86 static int pwm_nxp_s32_set_cycles_internal_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_internal_timebase() argument
94 return -EINVAL; in pwm_nxp_s32_set_cycles_internal_timebase()
97 if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
98 Emios_Pwm_Ip_SetPeriod(instance, channel, period_cycles); in pwm_nxp_s32_set_cycles_internal_timebase()
102 if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) { in pwm_nxp_s32_set_cycles_internal_timebase()
104 if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) { in pwm_nxp_s32_set_cycles_internal_timebase()
106 return -EIO; in pwm_nxp_s32_set_cycles_internal_timebase()
112 Emios_Pwm_Ip_ForceMatchTrailingEdge(instance, channel, true); in pwm_nxp_s32_set_cycles_internal_timebase()
120 static int pwm_nxp_s32_set_cycles_external_timebase(uint8_t instance, uint32_t channel, in pwm_nxp_s32_set_cycles_external_timebase() argument
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| D | pwm_gd32.c | 4 * SPDX-License-Identifier: Apache-2.0
36 /** Flag to indicate if timer has 32-bit counter */
50 /** Obtain channel enable bit for the given channel */
52 /** Obtain polarity bit for the given channel */
54 /** Obtain CHCTL0/1 mask for the given channel (0 or 1) */
60 static int pwm_gd32_set_cycles(const struct device *dev, uint32_t channel, in pwm_gd32_set_cycles() argument
64 const struct pwm_gd32_config *config = dev->config; in pwm_gd32_set_cycles() local
66 if (channel >= config->channels) { in pwm_gd32_set_cycles()
67 return -EINVAL; in pwm_gd32_set_cycles()
70 /* 16-bit timers can count up to UINT16_MAX */ in pwm_gd32_set_cycles()
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| D | pwm_rcar.c | 4 * SPDX-License-Identifier: Apache-2.0
30 #define RCAR_PWM_CR(channel) \ argument
31 ((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x00) /* PWM Control Register */
32 #define RCAR_PWM_CNT(channel) \ argument
33 ((uint32_t)((channel * RCAR_PWM_REG_SHIFT)) + 0x04) /* PWM Count Register */
41 #define RCAR_PWM_CR_EN BIT(0) /* Channel Enable */
50 #define RCAR_PWM_CNT_PH_MASK 0x000003ff /* PWM High-Level Period */
65 static uint32_t pwm_rcar_read(const struct pwm_rcar_cfg *config, uint32_t offs) in pwm_rcar_read() argument
67 return sys_read32(config->reg_addr + offs); in pwm_rcar_read()
70 static void pwm_rcar_write(const struct pwm_rcar_cfg *config, uint32_t offs, uint32_t value) in pwm_rcar_write() argument
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| D | pwm_b91.c | 4 * SPDX-License-Identifier: Apache-2.0
24 const struct pwm_b91_config *config = dev->config; in pwm_b91_init() local
31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1; in pwm_b91_init()
33 return -EINVAL; in pwm_b91_init()
39 /* Set PWM 32k Channel clock if enabled */ in pwm_b91_init()
40 clk_32k_en |= (config->clk32k_ch_enable & BIT(0)) ? PWM_CLOCK_32K_CHN_PWM0 : 0; in pwm_b91_init()
41 clk_32k_en |= (config->clk32k_ch_enable & BIT(1)) ? PWM_CLOCK_32K_CHN_PWM1 : 0; in pwm_b91_init()
42 clk_32k_en |= (config->clk32k_ch_enable & BIT(2)) ? PWM_CLOCK_32K_CHN_PWM2 : 0; in pwm_b91_init()
43 clk_32k_en |= (config->clk32k_ch_enable & BIT(3)) ? PWM_CLOCK_32K_CHN_PWM3 : 0; in pwm_b91_init()
44 clk_32k_en |= (config->clk32k_ch_enable & BIT(4)) ? PWM_CLOCK_32K_CHN_PWM4 : 0; in pwm_b91_init()
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| D | pwm_mcux_ftm.c | 3 * Copyright (c) 2020-2021 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
23 #define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
25 /* PWM capture operates on channel pairs */
57 ftm_chnl_pwm_config_param_t channel[MAX_CHANNELS]; member
64 static int mcux_ftm_set_cycles(const struct device *dev, uint32_t channel, in mcux_ftm_set_cycles() argument
68 const struct mcux_ftm_config *config = dev->config; in mcux_ftm_set_cycles() local
69 struct mcux_ftm_data *data = dev->data; in mcux_ftm_set_cycles()
72 uint32_t pair = channel / 2U; in mcux_ftm_set_cycles()
77 LOG_ERR("Channel can not be set to inactive level"); in mcux_ftm_set_cycles()
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| /Zephyr-latest/drivers/espi/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
22 module-str = espi
25 config ESPI_TARGET
31 config ESPI_INIT_PRIORITY
37 config ESPI_PERIPHERAL_CHANNEL
38 bool "eSPI peripheral channel"
41 eSPI Controller supports peripheral channel.
43 config ESPI_VWIRE_CHANNEL
44 bool "eSPI virtual wire channel"
47 eSPI Controller supports virtual wires channel.
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| D | Kconfig.xec | 4 # SPDX-License-Identifier: Apache-2.0
6 config ESPI_XEC
14 config ESPI_XEC_V2
24 config ESPI_OOB_CHANNEL
27 config ESPI_FLASH_CHANNEL
30 config ESPI_PERIPHERAL_HOST_IO
33 config ESPI_PERIPHERAL_HOST_IO_PVT
36 config ESPI_PERIPHERAL_DEBUG_PORT_80
39 config ESPI_PERIPHERAL_UART
42 config ESPI_PERIPHERAL_UART_SOC_MAPPING
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| /Zephyr-latest/drivers/dma/ |
| D | dma_xmc4xxx.c | 4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
54 int channel = find_lsb_set(channels_event) - 1; \
57 __ASSERT_NO_MSG(channel >= 0); \
58 dma_channel = &dev_data->channels[channel]; \
60 /* dma_start() and re-enable the event */ \
61 XMC_DMA_CH_ClearEventStatus(dma, channel, XMC_DMA_CH_##event_test); \
62 if (dma_channel->cb) { \
63 dma_channel->cb(dev, dma_channel->user_data, channel, (ret)); \
72 struct dma_xmc4xxx_data *dev_data = dev->data; in dma_xmc4xxx_isr()
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| D | dma_sedi.c | 4 * SPDX-License-Identifier: Apache-2.0
38 #define DEV_DATA(dev) ((struct dma_sedi_driver_data *const)(dev)->data)
40 ((const struct dma_sedi_config_info *const)(dev)->config)
46 static void dma_handler(sedi_dma_t dma_device, int channel, int event_id, in dma_handler() argument
52 struct dma_config *config = &(data->dma_configs[channel]); in dma_handler() local
54 /* run user-defined callback */ in dma_handler()
55 if (config->dma_callback) { in dma_handler()
57 (config->complete_callback_en)) { in dma_handler()
58 config->dma_callback(dev, config->user_data, in dma_handler()
59 channel, 0); in dma_handler()
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| D | dma_max32.c | 4 * SPDX-License-Identifier: Apache-2.0
36 /* mxc_dma_priority_t is limited to values 0-3 */ in max32_dma_ch_prio_valid()
38 LOG_ERR("Invalid DMA priority - must be type mxc_dma_priority_t (0-3)"); in max32_dma_ch_prio_valid()
54 LOG_ERR("Invalid DMA width - must be byte (1), halfword (2) or word (4)"); in max32_dma_width()
55 return -EINVAL; in max32_dma_width()
67 LOG_ERR("Invalid DMA address adjust - must be NO_CHANGE (0) or INCREMENT (1)"); in max32_dma_addr_adj()
77 static int max32_dma_config(const struct device *dev, uint32_t channel, struct dma_config *config) in max32_dma_config() argument
80 const struct max32_dma_config *cfg = dev->config; in max32_dma_config()
81 struct max32_dma_data *data = dev->data; in max32_dma_config()
84 if (channel >= cfg->channels) { in max32_dma_config()
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| D | dma_stm32_bdma.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
278 return -EAGAIN; in stm32_bdma_disable_channel()
288 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_dump_channel_irq() local
289 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_dump_channel_irq()
296 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_clear_channel_irq() local
297 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_clear_channel_irq()
306 const struct bdma_stm32_config *config = dev->config; in bdma_stm32_irq_handler() local
307 BDMA_TypeDef *dma = (BDMA_TypeDef *)(config->base); in bdma_stm32_irq_handler()
308 struct bdma_stm32_channel *channel; in bdma_stm32_irq_handler() local
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| D | dma_sam0.c | 4 * SPDX-License-Identifier: Apache-2.0
30 /* Handles DMA interrupts and dispatches to the individual channel */
33 struct dma_sam0_data *data = dev->data; in dma_sam0_isr()
35 uint16_t pend = DMA_REGS->INTPEND.reg; in dma_sam0_isr()
36 uint32_t channel; in dma_sam0_isr() local
38 /* Acknowledge all interrupts for the channel in pend */ in dma_sam0_isr()
39 DMA_REGS->INTPEND.reg = pend; in dma_sam0_isr()
41 channel = (pend & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; in dma_sam0_isr()
42 chdata = &data->channels[channel]; in dma_sam0_isr()
45 if (chdata->cb) { in dma_sam0_isr()
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| D | dma_emul.c | 4 * SPDX-License-Identifier: Apache-2.0
34 struct dma_config config; member
39 uint32_t channel; member
96 * channel state.
98 * Note: these must be called with data->lock locked!
101 uint32_t channel) in dma_emul_get_channel_state() argument
103 const struct dma_emul_config *config = dev->config; in dma_emul_get_channel_state() local
105 __ASSERT_NO_MSG(channel < config->num_channels); in dma_emul_get_channel_state()
107 return (enum dma_emul_channel_state)config->xfer[channel].config._reserved; in dma_emul_get_channel_state()
110 static void dma_emul_set_channel_state(const struct device *dev, uint32_t channel, in dma_emul_set_channel_state() argument
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| D | dma_si32.c | 4 * SPDX-License-Identifier: Apache-2.0
57 static void dma_si32_isr_handler(const uint8_t channel) in dma_si32_isr_handler() argument
59 const struct SI32_DMADESC_A_Struct *channel_descriptor = &channel_descriptors[channel]; in dma_si32_isr_handler()
60 const dma_callback_t cb = dma_si32_data.channel_data[channel].callback; in dma_si32_isr_handler()
61 void *user_data = dma_si32_data.channel_data[channel].callback_user_data; in dma_si32_isr_handler()
64 LOG_INF("Channel %" PRIu8 " ISR fired", channel); in dma_si32_isr_handler()
66 irq_disable(DMACH0_IRQn + channel); in dma_si32_isr_handler()
69 LOG_ERR("Bus error on channel %" PRIu8, channel); in dma_si32_isr_handler()
70 result = -EIO; in dma_si32_isr_handler()
73 __ASSERT(channel_descriptor->CONFIG.TMD == 0, "Result of success: TMD set to zero"); in dma_si32_isr_handler()
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| /Zephyr-latest/drivers/counter/ |
| D | counter_mcux_qtmr.c | 2 * Copyright (c) 2022 KT-Elektronik, Klaucke und Partner GmbH
3 * SPDX-License-Identifier: Apache-2.0
11 * Each quad timer module has four channels (0-3) that can operate independently, but the Zephyr
12 * counter-API does not support starting or stopping different channels independently. Hence, each
13 * channel is represented as an independent counter device.
32 qtmr_channel_selection_t channel; member
50 * @brief ISR for a specific timer channel
52 * @param dev timer channel device
56 const struct mcux_qtmr_config *config = dev->config; in mcux_qtmr_timer_handler() local
57 struct mcux_qtmr_data *data = dev->data; in mcux_qtmr_timer_handler()
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| D | counter_nxp_mrt.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * initialization, interrupt handling, and any other module-wide tasks. The current implementation
34 (*(struct nxp_mrt_channel_data *const *const)dev->data)
36 /* Device config->data is an array of data pointers ordered by channel number,
37 * dev->data is a pointer to one of these pointers in that array,
38 * so the value of the dev->data - dev->config->data is the channel index
41 (((struct nxp_mrt_channel_data *const *)dev->data) - \
42 ((const struct nxp_mrt_config *)dev->config)->data)
44 /* Specific for each channel */
65 const struct nxp_mrt_config *config = dev->config; in nxp_mrt_stop() local
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| D | counter_nxp_pit.c | 2 * Copyright 2020,2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
20 (*(struct nxp_pit_channel_data *const *const)dev->data)
22 /* Device config->data is an array of data pointers ordered by channel number,
23 * dev->data is a pointer to one of these pointers in that array,
24 * so the value of the dev->data - dev->config->data is the channel index
27 (((struct nxp_pit_channel_data *const *)dev->data) - \
28 ((const struct nxp_pit_config *)dev->config)->data)
56 const struct nxp_pit_config *config = dev->config; in nxp_pit_get_top_value() local
57 pit_chnl_t channel = PIT_CHANNEL_ID(dev); in nxp_pit_get_top_value() local
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| D | counter_nxp_s32_sys_timer.c | 2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
33 /* Channel Control */
37 /* Channel Interrupt */
41 /* Channel Compare */
47 #define REG_READ(r) sys_read32(config->base + (r))
48 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))
91 /* top is not 2^n-1 */ in ticks_add()
92 to_top = top - val1; in ticks_add()
94 return (val2 <= to_top) ? val1 + val2 : val2 - to_top; in ticks_add()
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