Searched full:ch4 (Results 1 – 19 of 19) sorted by relevance
| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | ledc_reg.h | 1757 * Ledc ch4 gamma ram write register.
1761 * Ledc ch4 gamma duty inc of current ram write address.This register is used to
1771 * Ledc ch4 gamma duty cycle of current ram write address.The duty will change every
1779 * Ledc ch4 gamma scale of current ram write address.This register is used to
1787 * Ledc ch4 gamma duty num of current ram write address.This register is used to
1796 * Ledc ch4 gamma ram write address register.
1800 * Ledc ch4 gamma ram write address.
1808 * Ledc ch4 gamma ram read address register.
1812 * Ledc ch4 gamma ram read address.
1820 * Ledc ch4 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 98 * Ledc ch4 duty change end event enable register, write 1 to enable this event.
123 * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event.
180 * Ledc ch4 duty scale update task enable register, write 1 to enable this task.
246 * Ledc ch4 signal out disable task enable register, write 1 to enable this task.
271 * Ledc ch4 overflow count reset task enable register, write 1 to enable this task.
337 * Ledc ch4 gamma restart task enable register, write 1 to enable this task.
362 * Ledc ch4 gamma pause task enable register, write 1 to enable this task.
387 * Ledc ch4 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 36 * ch4 enable
173 * ch4 set
310 * ch4 clear
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| D | soc_etm_reg.h | 47 * ch4 enable
276 * ch4 set
505 * ch4 clear
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| D | efuse_struct.h | 762 * ADC1 init code at atten0 ch4
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| D | efuse_reg.h | 979 * ADC1 init code at atten0 ch4
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | ledc_reg.h | 1757 * Ledc ch4 gamma ram write register.
1761 * Ledc ch4 gamma duty inc of current ram write address.This register is used to
1771 * Ledc ch4 gamma duty cycle of current ram write address.The duty will change every
1779 * Ledc ch4 gamma scale of current ram write address.This register is used to
1787 * Ledc ch4 gamma duty num of current ram write address.This register is used to
1796 * Ledc ch4 gamma ram write address register.
1800 * Ledc ch4 gamma ram write address.
1808 * Ledc ch4 gamma ram read address register.
1812 * Ledc ch4 gamma ram read address.
1820 * Ledc ch4 gamma ram read data register.
[all …]
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| D | ledc_struct.h | 98 * Ledc ch4 duty change end event enable register, write 1 to enable this event.
123 * Ledc ch4 overflow count pulse event enable register, write 1 to enable this event.
180 * Ledc ch4 duty scale update task enable register, write 1 to enable this task.
246 * Ledc ch4 signal out disable task enable register, write 1 to enable this task.
271 * Ledc ch4 overflow count reset task enable register, write 1 to enable this task.
337 * Ledc ch4 gamma restart task enable register, write 1 to enable this task.
362 * Ledc ch4 gamma pause task enable register, write 1 to enable this task.
387 * Ledc ch4 gamma resume task enable register, write 1 to enable this task.
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| D | soc_etm_struct.h | 36 * ch4 enable
173 * ch4 set
310 * ch4 clear
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| D | soc_etm_reg.h | 47 * ch4 enable
276 * ch4 set
505 * ch4 clear
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| /hal_espressif-latest/zephyr/port/pincfgs/ |
| D | esp32c2.yml | 86 ch4:
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| D | esp32c3.yml | 138 ch4:
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| D | esp32c6.yml | 91 ch4:
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| D | esp32s2.yml | 171 ch4:
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| D | esp32.yml | 198 ch4:
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| D | esp32s3.yml | 197 ch4:
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| /hal_espressif-latest/components/efuse/esp32c6/ |
| D | esp_efuse_table.csv | 190 …1_INIT_CODE_ATTEN0_CH4, EFUSE_BLK2, 241, 4, [] ADC1 init code at atten0 ch4
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| D | esp_efuse_table.c | 705 {EFUSE_BLK2, 241, 4}, // [] ADC1 init code at atten0 ch4,
1613 &ADC1_INIT_CODE_ATTEN0_CH4[0], // [] ADC1 init code at atten0 ch4
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| /hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/ |
| D | esp32c6.yaml | 98 … : '', dict : '', desc: ADC1 init code at atten0 ch4, rloc: 'EFUSE_RD_SY…
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