/Zephyr-latest/tests/cmake/zephyr_get/ |
D | CMakeLists.txt | 30 set(ASSERT_FAIL_COUNT 0 CACHE INTERNAL "") 36 if($CACHE{ASSERT_FAIL_COUNT} GREATER 0) 42 message(${mode} "$CACHE{ASSERT_FAIL_COUNT} assertion(s) failed") 91 math(EXPR ASSERT_FAIL_COUNT "$CACHE{ASSERT_FAIL_COUNT} + 1") 92 set(ASSERT_FAIL_COUNT ${ASSERT_FAIL_COUNT} CACHE INTERNAL "") 100 set(VARIABLE "cmake cache" CACHE INTERNAL "") 103 # CMake cache value has the highest precedence. 105 assert_equal(VARIABLE "cmake cache") 108 unset(VARIABLE CACHE) 115 assert_equal(CACHE{VARIABLE} "environment") [all …]
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/Zephyr-latest/subsys/net/lib/dns/ |
D | dns_cache.c | 12 static void dns_cache_clean(struct dns_cache const *cache); 14 int dns_cache_flush(struct dns_cache *cache) in dns_cache_flush() argument 16 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_flush() 17 for (size_t i = 0; i < cache->size; i++) { in dns_cache_flush() 18 cache->entries[i].in_use = false; in dns_cache_flush() 20 k_mutex_unlock(cache->lock); in dns_cache_flush() 25 int dns_cache_add(struct dns_cache *cache, char const *query, struct dns_addrinfo const *addrinfo, in dns_cache_add() argument 32 if (cache == NULL || query == NULL || addrinfo == NULL || ttl == 0) { in dns_cache_add() 43 k_mutex_lock(cache->lock, K_FOREVER); in dns_cache_add() 47 dns_cache_clean(cache); in dns_cache_add() [all …]
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D | dns_cache.h | 2 * @brief DNS cache 4 * An cache holding dns records for faster dns resolving. 37 * The cache can be accessed outside the module where it is defined using: 41 * @param name Name of the cache. 50 * @brief Flushes the dns cache removing all its entries. 52 * @param cache Cache to be flushed 56 int dns_cache_flush(struct dns_cache *cache); 59 * @brief Adds a new entry to the dns cache removing the one closest to expiry 62 * @param cache Cache where the entry should be added. 63 * @param query Query which should be persisted in the cache. [all …]
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/Zephyr-latest/include/zephyr/drivers/ |
D | cache.h | 9 * Public APIs for external cache controller drivers 18 * @brief External Cache Controller Interface 19 * @defgroup cache_external_interface External Cache Controller Interface 31 * @brief Enable the d-cache 33 * Enable the data cache. 38 * @brief Disable the d-cache 40 * Disable the data cache. 45 * @brief Flush the d-cache 47 * Flush the whole data cache. 56 * @brief Invalidate the d-cache [all …]
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/Zephyr-latest/include/zephyr/arch/ |
D | cache.h | 9 * Public APIs for architectural cache controller drivers 16 * @brief Cache Controller Interface 17 * @defgroup cache_arch_interface Cache Controller Interface 23 #include <zephyr/arch/arm64/cache.h> 25 #include <zephyr/arch/xtensa/cache.h> 31 * @brief Enable the d-cache 33 * Enable the data cache. 40 * @brief Disable the d-cache 42 * Disable the data cache. 49 * @brief Flush the d-cache [all …]
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/Zephyr-latest/soc/espressif/esp32s3/ |
D | Kconfig | 17 menu "Cache config" 20 prompt "Instruction cache size" 23 Instruction cache size to be set on application startup. 24 If you use 16KB instruction cache rather than 32KB instruction cache, 39 prompt "Instruction cache associated ways" 42 Instruction cache associated ways to be set on application startup. 56 prompt "Instruction cache line size" 59 Instruction cache line size to be set on application startup. 74 bool "Define instruction cache wrap mode" 76 If enabled, instruction cache will use wrap mode to read spi flash or spi ram. [all …]
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/Zephyr-latest/doc/hardware/cache/ |
D | index.rst | 3 Cache Control Configuration 6 This is a high-level guide to Zephyr's cache interface and Kconfig options related to 7 cache controllers. See :ref:`cache_api` for API reference material. 9 Zephyr has different Kconfig options to control how the cache controller is 15 instruction cache. The cache controller can be in the core or can be an 16 external cache controller for which a driver is provided. 19 should be set whether we plan to support and use the cache control in Zephyr 23 options must be selected when support for data or instruction cache is 27 All the code paths related to cache control must be conditionally enabled 28 depending on these symbols. When the symbol is set the cache is considered [all …]
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D | guide.rst | 6 This section discusses the basics of cache coherency and under what situations a 10 data cache though there is typically also an instruction cache for systems with 11 cache support. 20 While cache coherence can be a concern for data shared between SMP cores, Zephyr 22 cores. Most applications will only need to use the cache APIs for interaction 24 different OS image. For more information on cache coherence between SMP cores, 28 cache coherency needs to be considered. Typically processor caches exist as 31 processor's cache, resulting in what appears to be corrupt data. If you are 32 moving data using DMA and the processor doesn't see the data you expect, cache 37 this defeats the purpose of having a hardware cache in the first place and [all …]
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/Zephyr-latest/drivers/cache/ |
D | Kconfig | 4 menuconfig CACHE config 5 bool "External cache controller drivers" 8 Enable support for external cache controllers drivers 10 if CACHE 15 module = CACHE 16 module-str = cache 21 source "drivers/cache/Kconfig.aspeed" 22 source "drivers/cache/Kconfig.nrf" 23 source "drivers/cache/Kconfig.andes" 25 endif # CACHE
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D | cache_nrf.c | 7 #include <zephyr/drivers/cache.h> 44 static inline bool is_cache_busy(NRF_CACHE_Type *cache) in is_cache_busy() argument 47 return nrf_cache_busy_check(cache); in is_cache_busy() 53 static inline void wait_for_cache(NRF_CACHE_Type *cache) in wait_for_cache() argument 55 while (is_cache_busy(cache)) { in wait_for_cache() 59 static inline int _cache_all(NRF_CACHE_Type *cache, enum k_nrf_cache_op op) in _cache_all() argument 62 * We really do not want to invalidate the whole cache. in _cache_all() 68 wait_for_cache(cache); in _cache_all() 74 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_CLEANCACHE); in _cache_all() 79 nrf_cache_task_trigger(cache, NRF_CACHE_TASK_INVALIDATECACHE); in _cache_all() [all …]
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D | Kconfig.andes | 6 bool "ANDES external cache driver" 11 This option enables the CACHE driver for ANDES V5 series SOC. 19 When L2 cache is inclusive of L1, CPU only needs to perform operations 20 on L2 cache, instead of on both L1 and L2 caches. 23 int "Andes cache driver init priority" 26 This option controls the priority of the cache initialization.
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/Zephyr-latest/subsys/logging/ |
D | log_cache.h | 39 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config); 43 * @param[in] cache Cache object. 50 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data); 52 /** @brief Put new entry into cache. 54 * @param cache Cache object. 58 void log_cache_put(struct log_cache *cache, uint8_t *data); 63 * not found in the cache. Releasing puts entry in idle list. 65 * @param cache Cache object. 68 void log_cache_release(struct log_cache *cache, uint8_t *data); 72 * @param cache Cache object. [all …]
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D | log_cache.c | 24 int log_cache_init(struct log_cache *cache, const struct log_cache_config *config) in log_cache_init() argument 26 sys_slist_init(&cache->active); in log_cache_init() 27 sys_slist_init(&cache->idle); in log_cache_init() 34 /* Ensure the cache has at least one entry */ in log_cache_init() 41 sys_slist_append(&cache->idle, &entry->node); in log_cache_init() 45 cache->cmp = config->cmp; in log_cache_init() 46 cache->item_size = config->item_size; in log_cache_init() 47 cache->hit = 0; in log_cache_init() 48 cache->miss = 0; in log_cache_init() 53 bool log_cache_get(struct log_cache *cache, uintptr_t id, uint8_t **data) in log_cache_get() argument [all …]
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/Zephyr-latest/tests/subsys/logging/log_cache/src/ |
D | main.c | 61 static void cache_get(struct log_cache *cache, uintptr_t id, in cache_get() argument 64 uint32_t hit = log_cache_get_hit(cache); in cache_get() 65 uint32_t miss = log_cache_get_miss(cache); in cache_get() 68 res = log_cache_get(cache, id, buf); in cache_get() 71 zassert_equal(hit + 1, log_cache_get_hit(cache), "line %u\n", line); in cache_get() 72 zassert_equal(miss, log_cache_get_miss(cache), "line %u\n", line); in cache_get() 74 zassert_equal(hit, log_cache_get_hit(cache), "line %u\n", line); in cache_get() 75 zassert_equal(miss + 1, log_cache_get_miss(cache), "line %u\n", line); in cache_get() 91 struct log_cache cache; in ZTEST() local 105 err = log_cache_init(&cache, &config); in ZTEST() [all …]
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/Zephyr-latest/include/zephyr/ |
D | cache.h | 13 * @brief cache API interface 25 #include <zephyr/drivers/cache.h> 28 #include <zephyr/arch/cache.h> 33 * @defgroup cache_interface Cache Interface 48 * @brief Enable the d-cache 50 * Enable the data cache 61 * @brief Disable the d-cache 63 * Disable the data cache 74 * @brief Enable the i-cache 76 * Enable the instruction cache [all …]
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/Zephyr-latest/dts/riscv/starfive/ |
D | jh7110-visionfive-v2.dtsi | 38 d-cache-block-size = <64>; 39 d-cache-sets = <64>; 40 d-cache-size = <32768>; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 49 next-level-cache = <&ccache>; 63 d-cache-block-size = <64>; 64 d-cache-sets = <64>; 65 d-cache-size = <32768>; [all …]
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D | starfive_jh7100_beagle_v.dtsi | 23 d-cache-block-size = <64>; 24 d-cache-sets = <64>; 25 d-cache-size = <32768>; 29 i-cache-block-size = <64>; 30 i-cache-sets = <64>; 31 i-cache-size = <32768>; 35 next-level-cache = <&cachectrl>; 52 d-cache-block-size = <64>; 53 d-cache-sets = <64>; 54 d-cache-size = <32768>; [all …]
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/Zephyr-latest/soc/espressif/esp32s2/ |
D | Kconfig | 17 menu "Cache config" 20 prompt "Instruction cache line size" 32 prompt "Instruction cache size" 36 bool "8KB instruction cache size" 39 bool "16KB instruction cache size" 44 prompt "Data cache size" 47 Data cache size to be set on application startup. 59 prompt "Data cache line size" 81 endmenu # Cache config
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/Zephyr-latest/cmake/modules/ |
D | user_cache.cmake | 5 # Configure user cache directory. 7 # The user cache can be used for caching of data that should be persistent 11 # Only data that can be safely re-generated should be placed in this cache. 13 # Zephyr build system uses this user cache to store Zephyr compiler check 20 # - USER_CACHE_DIR: User cache directory in use. 33 set(env_suffix_LOCALAPPDATA .cache) 36 # On macOS, ~/Library/Caches is the preferred cache directory. 39 set(env_suffix_HOME .cache) 51 # that is defined and defaulting to $HOME/.cache otherwise. 83 # Zephyr's cache files go in the "zephyr" subdirectory of the [all …]
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/Zephyr-latest/arch/nios2/core/ |
D | cache.c | 12 * Flush the entire instruction cache and pipeline. 16 * new text was written with instructions that do not bypass cache memories, 22 * information on cache considerations. 39 * Flush the entire data cache. 42 * after flushing the instruction cache. 44 * The Nios II does not support hardware cache coherency for multi-master 47 * in Zephyr additional APIs for flushing ranges of the data cache will need 51 * information on cache considerations. 65 * z_nios2_dcache_flush_no_writeback() is called to flush the data cache for a 68 * Any dirty lines in the data cache are NOT written back to memory.
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/Zephyr-latest/lib/os/ |
D | Kconfig | 49 prompt "Cache handling" 55 bool "Use cache flag" 57 Use instance specific configuration flag for cache handling. 60 bool "Always handle cache" 62 Handle cache writeback and invalidation for all instances. Option used 68 bool "Never handle cache" 70 Discar cache handling for all instances. Option used to avoid runtime 84 int "Remote cache line size" 88 this value should be set to the data cache line size of the remote core. 89 If local data cache line is detected at runtime then it should be
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/Zephyr-latest/scripts/tests/twister/ |
D | test_cmakecache.py | 182 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt') 184 assert cache.cache_file == 'dummy/path/CMakeCache.txt' 193 item = cache._entries.popitem() 204 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt') 206 good_val = cache.get('DUMMY_NAME') 210 bad_val = cache.get('ANOTHER_NAME') 214 bad_val = cache.get('ANOTHER_NAME', default='No such value') 237 cache = CMakeCache.from_file('dummy/path/CMakeCache.txt') 242 res = cache.get_list('DUMMY_NAME') if \ 243 correct_get else cache.get_list('ANOTHER_NAME') [all …]
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/Zephyr-latest/.github/workflows/ |
D | devicetree_checks.yml | 38 - name: cache-pip-linux 40 uses: actions/cache@v4 42 path: ~/.cache/pip 46 - name: cache-pip-mac 48 uses: actions/cache@v4 51 # Trailing '-' was just to get a different cache name 55 - name: cache-pip-win 57 uses: actions/cache@v4 59 path: ~\AppData\Local\pip\Cache
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D | west_cmds.yml | 41 - name: cache-pip-linux 43 uses: actions/cache@v4 45 path: ~/.cache/pip 49 - name: cache-pip-mac 51 uses: actions/cache@v4 54 # Trailing '-' was just to get a different cache name 58 - name: cache-pip-win 60 uses: actions/cache@v4 62 path: ~\AppData\Local\pip\Cache
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/Zephyr-latest/subsys/fs/zms/ |
D | Kconfig | 16 bool "ZMS lookup cache" 18 Enable ZMS cache to reduce the ZMS data lookup time. 19 Each cache entry holds an address of the most recent allocation 20 table entry (ATE) for all ZMS IDs that fall into that cache position. 23 int "ZMS Storage lookup cache size" 28 Number of entries in ZMS lookup cache. 30 Every additional entry in cache will add 8 bytes in RAM
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