Lines Matching full:cache

6 This section discusses the basics of cache coherency and under what situations a
10 data cache though there is typically also an instruction cache for systems with
11 cache support.
20   While cache coherence can be a concern for data shared between SMP cores, Zephyr
22   cores. Most applications will only need to use the cache APIs for interaction
24   different OS image. For more information on cache coherence between SMP cores,
28 cache coherency needs to be considered. Typically processor caches exist as
31 processor's cache, resulting in what appears to be corrupt data. If you are
32 moving data using DMA and the processor doesn't see the data you expect, cache
37 this defeats the purpose of having a hardware cache in the first place and
39 disabling caching for only a portion of memory. This can be useful when cache
41 Finally, there is the option to flush or invalidate the cache for regions of
44 Globally Disabling the Data Cache
54 * :kconfig:option:`CONFIG_CACHE_MANAGEMENT`: cache API enabled.
56 * Call :c:func:`sys_cache_data_disable()` to globally disable the data cache.
64 unrelated buffers that are smaller than a cache line.
124 Runtime Cache Control
128 runtime. The two most relevant cache operations in this case are **flushing**
130 cacheable memory, the cache line. Data cache lines are typically 16 to 128
131 bytes. See :kconfig:option:`CONFIG_DCACHE_LINE_SIZE`. Cache line sizes are
133 the size of cache lines in order to correctly and efficiently manage the cache.
134 If the buffers in question are smaller than the data cache line size, it may be
136 into the same cache line may be destroyed when invalidating.
138 Flushing the cache involves writing all modified cache lines in a specified
139 region back to shared memory. Flush the cache associated with a buffer after the
145   Some architectures support a cache configuration called **write-through**
147   shared memory. While this solves the cache coherence problem for CPU writes,
151 Invalidating the cache works similarly but in the other direction. It marks
152 cache lines in the specified region as stale, ensuring that the cache line will
154 region. Invalidate the data cache of a buffer that a peripheral has written to
158 In that case it is possible to first flush the cache associated with a buffer
159 and then invalidate it, ensuring that the cache will be refreshed the next time
166 * :kconfig:option:`CONFIG_CACHE_MANAGEMENT`: cache API enabled.
178 buffers should be aligned to the cache line size. This can be accomplished by