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/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
23 means that normally xgmac will reject any frame above max-frame-size
27 max-speed:
30 - 10
31 - 100
32 - 1000
33 - 2500
[all …]
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
[all …]
/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
[all …]
/Zephyr-latest/drivers/i2s/
DKconfig.mcux4 # SPDX-License-Identifier: Apache-2.0
18 int "RX queue length"
22 int "TX queue length"
26 int "I2S EDMA BURST SIZE"
29 I2S EDMA burst size in bytes.
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_mcux_pxp.h2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
24 * source burst length: height of source buffer in pixels
26 * dest burst length: height of destination buffer in pixels
Ddma_mcux_lpc.h4 * SPDX-License-Identifier: Apache-2.0
37 /* HW trigger burst mode. When set, the hardware trigger will cause a burst
38 * transfer to occur, the length of which is determined by BURST_POWER.
44 /* HW trigger burst power. Note that due to the size limit of the dma_slot
45 * field, the maximum transfer burst possible is 128. The hardware supports
/Zephyr-latest/drivers/dma/
Ddma_pl330.h4 * SPDX-License-Identifier: Apache-2.0
14 * Max burst length and max burst size for 32bit system with
17 * Burst length is encoded in following format for pl330
25 * Burst size is encoded in following format for pl330
DKconfig.dw_axi_dmac4 # SPDX-License-Identifier: Apache-2.0
27 This flag can be enabled if hardware support Linked List multi-block transfer
36 int "max burst transaction length"
Ddma_stm32_v1.c4 * SPDX-License-Identifier: Apache-2.0
17 /* DMA burst length */
362 memory_burst = config->dest_burst_length; in stm32_dma_get_mburst()
364 memory_burst = config->source_burst_length; in stm32_dma_get_mburst()
377 LOG_ERR("Memory burst size error," in stm32_dma_get_mburst()
378 "using single burst as default"); in stm32_dma_get_mburst()
388 periph_burst = config->source_burst_length; in stm32_dma_get_pburst()
390 periph_burst = config->dest_burst_length; in stm32_dma_get_pburst()
403 LOG_ERR("Peripheral burst size error," in stm32_dma_get_pburst()
404 "using single burst as default"); in stm32_dma_get_pburst()
[all …]
Ddma_dw_axi.c4 * SPDX-License-Identifier: Apache-2.0
17 #define DEV_CFG(_dev) ((const struct dma_dw_axi_dev_cfg *)(_dev)->config)
18 #define DEV_DATA(_dev) ((struct dma_dw_axi_dev_data *const)(_dev)->data)
29 #define DMA_DW_AXI_GET_MSIZE(blen) ((blen == 1) ? (0U) : (find_msb_set(blen) - 2U))
91 /* bitfield configuration for multi-block transfer */
117 /* source burst length enable */
119 /* source burst length(considered when corresponding enable bit is set) */
121 /* destination burst length enable */
123 /* destination burst length(considered when corresponding enable bit is set) */
126 /* source burst transaction length */
[all …]
Ddma_mcux_pxp.c2 * Copyright 2023-2024 NXP
5 * SPDX-License-Identifier: Apache-2.0
38 const struct dma_mcux_pxp_config *config = dev->config; in dma_mcux_pxp_irq_handler()
39 struct dma_mcux_pxp_data *data = dev->data; in dma_mcux_pxp_irq_handler()
41 PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag); in dma_mcux_pxp_irq_handler()
43 DCACHE_InvalidateByRange((uint32_t)data->out_buf_addr, data->out_buf_size); in dma_mcux_pxp_irq_handler()
45 if (data->dma_callback) { in dma_mcux_pxp_irq_handler()
46 data->dma_callback(dev, data->user_data, 0, 0); in dma_mcux_pxp_irq_handler()
54 const struct dma_mcux_pxp_config *dev_config = dev->config; in dma_mcux_pxp_configure()
55 struct dma_mcux_pxp_data *dev_data = dev->data; in dma_mcux_pxp_configure()
[all …]
Ddma_silabs_ldma.c4 * SPDX-License-Identifier: Apache-2.0
68 LOG_ERR("Source burst length (%u) and destination burst length(%u) must be equal", in dma_silabs_get_blocksize()
70 return -ENOTSUP; in dma_silabs_get_blocksize()
74 LOG_ERR("burst length (%u) and data size (%u) mismatch", src_blen, dst_blen); in dma_silabs_get_blocksize()
75 return -EINVAL; in dma_silabs_get_blocksize()
85 return -EINVAL; in dma_silabs_get_blocksize()
94 if (block->dest_scatter_count || block->source_gather_count || in dma_silabs_block_to_descriptor()
95 block->source_gather_interval || block->dest_scatter_interval || in dma_silabs_block_to_descriptor()
96 block->dest_reload_en || block->source_reload_en) { in dma_silabs_block_to_descriptor()
97 return -ENOTSUP; in dma_silabs_block_to_descriptor()
[all …]
Ddma_nxp_edma.c4 * SPDX-License-Identifier: Apache-2.0
16 * 5) Ideally, HALFMAJOR should be set on a per-channel basis not through a
30 cfg = chan->dev->config; in edma_isr()
31 data = chan->dev->data; in edma_isr()
33 if (chan->state == CHAN_STATE_RELEASING || chan->state == CHAN_STATE_INIT) { in edma_isr()
38 if (!EDMA_ChannelRegRead(data->hal_cfg, chan->id, EDMA_TCD_CH_INT)) { in edma_isr()
44 EDMA_ChannelRegUpdate(data->hal_cfg, chan->id, in edma_isr()
47 if (chan->cyclic_buffer) { in edma_isr()
48 update_size = chan->bsize; in edma_isr()
51 update_size = chan->bsize / 2; in edma_isr()
[all …]
Ddma_sam0.c4 * SPDX-License-Identifier: Apache-2.0
33 struct dma_sam0_data *data = dev->data; in dma_sam0_isr()
35 uint16_t pend = DMA_REGS->INTPEND.reg; in dma_sam0_isr()
39 DMA_REGS->INTPEND.reg = pend; in dma_sam0_isr()
42 chdata = &data->channels[channel]; in dma_sam0_isr()
45 if (chdata->cb) { in dma_sam0_isr()
46 chdata->cb(dev, chdata->user_data, in dma_sam0_isr()
47 channel, -DMAC_INTPEND_TERR); in dma_sam0_isr()
50 if (chdata->cb) { in dma_sam0_isr()
51 chdata->cb(dev, chdata->user_data, channel, 0); in dma_sam0_isr()
[all …]
Ddma_esp32_gdma.c4 * SPDX-License-Identifier: Apache-2.0
83 struct dma_esp32_data *data = (struct dma_esp32_data *const)(dev)->data; in dma_esp32_isr_handle_rx()
86 gdma_ll_rx_clear_interrupt_status(data->hal.dev, rx->channel_id, intr_status); in dma_esp32_isr_handle_rx()
97 status = -intr_status; in dma_esp32_isr_handle_rx()
100 if (rx->cb) { in dma_esp32_isr_handle_rx()
101 rx->cb(dev, rx->user_data, rx->channel_id * 2, status); in dma_esp32_isr_handle_rx()
108 struct dma_esp32_data *data = (struct dma_esp32_data *const)(dev)->data; in dma_esp32_isr_handle_tx()
110 gdma_ll_tx_clear_interrupt_status(data->hal.dev, tx->channel_id, intr_status); in dma_esp32_isr_handle_tx()
114 if (tx->cb) { in dma_esp32_isr_handle_tx()
115 tx->cb(dev, tx->user_data, tx->channel_id * 2 + 1, -intr_status); in dma_esp32_isr_handle_tx()
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi_aps6408l.c4 * SPDX-License-Identifier: Apache-2.0
28 read-while-write hazards. This configuration is not recommended."
52 /* Burst type/burst length mask (MR8[0:2]) */
57 #define APS_6408L_ROW_CROSS_EN 0x8 /* Enable linear burst reads to cross rows */
84 /* Read Data (Sync read, linear burst) */
91 /* Write Data (Sync write, linear burst) */
123 const struct memc_flexspi_aps6408l_config *config = dev->config; in memc_flexspi_aps6408l_get_vendor_id()
124 struct memc_flexspi_aps6408l_data *data = dev->data; in memc_flexspi_aps6408l_get_vendor_id()
130 .port = config->port, in memc_flexspi_aps6408l_get_vendor_id()
138 ret = memc_flexspi_transfer(data->controller, &transfer); in memc_flexspi_aps6408l_get_vendor_id()
[all …]
/Zephyr-latest/drivers/ethernet/dwc_xgmac/
Deth_dwc_xgmac_priv.h7 * SPDX-License-Identifier: Apache-2.0
467 * the EDMA starts pre-fetching the TxDMA descriptors
471 * the EDMA starts pre-fetching the RxDMA descriptors
474 /* Mixed burst: AXI master can perform burst transfers that are equal to or
475 * less than the maximum allowed burst length programmed
478 /* burst length 4bytes */
480 /* burst length 8bytes */
482 /* burst length 16bytes */
484 /* burst length 32bytes */
486 /* burst length 64bytes */
[all …]
/Zephyr-latest/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
[all …]
Dzynq7000.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-a.dtsi>
8 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
13 interrupt-parent = <&gic>;
16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
18 zephyr,memory-region = "OCM_LOW";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
24 zephyr,memory-region = "OCM_HIGH";
28 compatible = "arm,armv8-timer";
[all …]
/Zephyr-latest/include/zephyr/drivers/
Ddma.h10 * SPDX-License-Identifier: Apache-2.0
137 * - 0b00 increment
138 * - 0b01 decrement
139 * - 0b10 no change
145 * - 0b00 increment
146 * - 0b01 decrement
147 * - 0b10 no change
159 * - 0b0 source request service upon data availability
160 * - 0b1 source request postponed until destination request happens
185 * - DMA_STATUS_COMPLETE buffer fully consumed
[all …]
Dmipi_dsi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DSI drivers
16 * @brief MIPI-DSI driver APIs
17 * @defgroup mipi_dsi_interface MIPI-DSI driver APIs
27 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
33 /** MIPI-DSI display timings. */
41 /** Horizontal sync length. */
49 /** Vertical sync length. */
54 * @name MIPI-DSI Device mode flags.
60 /** Video burst mode */
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h2 * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
3 * SPDX-License-Identifier: Apache-2.0
9 /* PHY auto-detection alias */
17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
23 * on the UltraScale compared to the Zynq-7000.
24 * -> Contrary to earlier revisions of this driver, all dividers are available
25 * to both the UltraScale and the Zynq-7000.
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
57 * [12 .. 00] Data length of received frame
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
86 * exhausted mid-frame
91 * [13 .. 00] Data length in the BD's associated buffer
[all …]
Deth_cyclonev.c2 * SPDX-License-Identifier: Apache-2.0
5 * 3504-0 Universal 10/100/1000 Ethernet MAC (DWC_gmac)
9 * https://github.com/altera-opensource/intel-socfpga-hwlib
71 * /us/en/pdfs/literature/hb/cyclone-v/cv_54001.pdf p. 1252
135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()
156 return -1; in eth_cyclonev_get_software_reset_status()
158 return EMAC_DMA_MODE_SWR_GET(sys_read32(EMAC_DMAGRP_BUS_MODE_ADDR(p->base_addr))); in eth_cyclonev_get_software_reset_status()
167 * @retval 0 if Reset was successful, -1 otherwise
175 return -1; in eth_cyclonev_software_reset()
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc1200.h1 /* ieee802154_cc1200.h - Registers definition for TI CC1200 */
6 * SPDX-License-Identifier: Apache-2.0
25 * CHIP -> EM adapter
26 * GPIO0 -> GPIOA
27 * GPIO1 -> reserved (it's SPI MISO)
28 * GPIO2 -> GPIOB
29 * GPIO3 -> GPIO3
66 void *data, size_t length, bool extended, bool burst);

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