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/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_reg.h138 /* Bank0 #define REG_DEVICE_CONFIG_REG */
141 /* Bank0 #define REG_GYRO_CONFIG0, REG_ACCEL_CONFIG0 */
146 /* Bank0 #define REG_GYRO_CONFIG1 */
163 /* Bank0 REG_ACCEL_CONFIG1 */
173 /* Bank0 REG_INT_CONFIG_REG */
178 /* Bank0 REG_PWR_MGMT_0 */
189 /* Bank0 REG_SIGNAL_PATH_RESET */
198 /* Bank0 REG_INTF_CONFIG0 */
205 /* Bank0 REG_INTF_CONFIG1 */
218 /* Bank0 REG_FIFO_CONFIG1 */
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_reg.h127 /* Bank0 REG_DEVICE_CONFIG */
131 /* Bank0 REG_DRIVE_CONFIG */
134 /* Bank0 REG_INT_CONFIG */
142 /* Bank0 REG_FIFO_CONFIG */
148 /* Bank0 REG_INT_STATUS */
157 /* Bank0 REG_INT_STATUS2 */
163 /* Bank0 REG_INT_STATUS3 */
170 /* Bank0 REG_SIGNAL_PATH_RESET */
177 /* Bank0 REG_INTF_CONFIG0 */
186 /* Bank0 REG_INTF_CONFIG1 */
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dgd,gd32-nv-flash-v2.yaml23 bank0-page-size:
26 description: Flash memory page size for bank0
/Zephyr-latest/drivers/flash/
Dflash_gd32_v2.c21 * Bank0 holds the first 512KB, bank1 is used give capacity for reset.
37 * Bank0 holds the first 256KB, bank1 is used give capacity for reset.
122 LOG_ERR("FMC bank0 programming failed"); in gd32_fmc_v2_bank0_write()
157 LOG_ERR("FMC bank0 page %u erase failed", page_addr); in gd32_fmc_v2_bank0_page_erase()
329 /* Remove bank0 info from offset and len. */ in flash_gd32_valid_range()
373 /* Will programming bank1, remove bank0 offset. */ in flash_gd32_write_range()
412 /* Will programming bank1, remove bank0 info from offset. */ in flash_gd32_erase_block()
/Zephyr-latest/tests/drivers/flash/common/boards/
Dgd32a503v_eval.overlay13 /* Set 4KB of storage at the border of bank0(256KB) and bank1(128KB). */
/Zephyr-latest/dts/bindings/flash_controller/
Dgd,gd32-flash-controller.yaml12 registers to control bank0 and bank1 separately.
/Zephyr-latest/arch/arc/core/
Disr_wrapper.S135 using bank0 of registers, since that is where the registers containing
165 When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
167 bank0, and now has to load the incoming one into bank0.
Dfast_irq.S109 * change bank1's sp, not bank0's sp
200 * the sp of user stack of interrupted thread is reg bank0'sp
Dfault_s.S142 * register bank0 (if exception is raised in firq with 2 reg
Dirq_manage.c69 /* switch back to bank0, use ilink to avoid the pollution of in z_arc_firq_stack_set()
/Zephyr-latest/drivers/bbram/
Dbbram_it8xxx2.c92 * entire Bank0 and Bank1 BRAM, and set magic value. in bbram_it8xxx2_init()
/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h33 /* Bank0, Offset 0x6: Counter Register */
/Zephyr-latest/drivers/gpio/
Dgpio_ambiq.c523 /* Apollo3 GPIO banks share the same irq number, connect to bank0 once when init and handle in ambiq_gpio_cfg_func()
534 /* Shared irq config default to BANK0. */ in ambiq_gpio_cfg_func()
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi69 bank0-page-size = <DT_SIZE_K(1)>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi68 bank0-page-size = <DT_SIZE_K(2)>;