Searched +full:bank0 +full:- +full:page +full:- +full:size (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-latest/dts/bindings/mtd/ |
| D | gd,gd32-nv-flash-v2.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 - GD32F10x
9 - GD32F20x
10 - GD32F30x
11 - GD32F403
13 include: soc-nv-flash.yaml
15 compatible: gd,gd32-nv-flash-v2
18 max-erase-time-ms:
21 description: Max erase time(millisecond) of a flash page
23 bank0-page-size:
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| /Zephyr-latest/dts/bindings/flash_controller/ |
| D | gd,gd32-flash-controller.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 GD32 FMC v1: its flash memory has 1 bank, page size is equal in the bank,
8 flash size is smaller than 512KB.
10 GD32 FMC v2: its flash memory has 2 banks. Page size equal within the same bank but
11 different between banks. Flash size can be up to 3072KB. FMC v2 has two
12 registers to control bank0 and bank1 separately.
14 GD32 FMC v3: its flash memory has 2 banks, use sector size as the minimum operating
15 unit, the sector size is not equal.
17 compatible: "gd,gd32-flash-controller"
19 include: flash-controller.yaml
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| /Zephyr-latest/drivers/flash/ |
| D | flash_gd32_v2.c | 4 * SPDX-License-Identifier: Apache-2.0
21 * Bank0 holds the first 512KB, bank1 is used give capacity for reset.
22 * The page size is the same within the same bank, but not equal for all banks.
30 #define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(512))
37 * Bank0 holds the first 256KB, bank1 is used give capacity for reset.
38 * The page size is 1KB for all banks.
46 #define GD32_NV_FLASH_V2_BANK1_SIZE (SOC_NV_FLASH_SIZE - KB(256))
89 return -ETIMEDOUT; in gd32_fmc_v2_bank0_wait_idle()
105 return -EBUSY; in gd32_fmc_v2_bank0_write()
120 ret = -EIO; in gd32_fmc_v2_bank0_write()
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| /Zephyr-latest/dts/arm/gd/gd32a50x/ |
| D | gd32a50x.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32a50x-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32a50x.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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| /Zephyr-latest/dts/arm/gd/gd32f403/ |
| D | gd32f403.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
14 #include <zephyr/dt-bindings/reset/gd32f403.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
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