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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dhsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
18 clock-frequency = <DT_FREQ_M(16)>;
19 ahb-prescaler = <1>;
20 apb1-prescaler = <1>;
21 apb2-prescaler = <1>;
22 apb3-prescaler = <1>;
Dmsis_24.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <1>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(24)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dmsis_48.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <0>;
19 msi-pll-mode;
24 clock-frequency = <DT_FREQ_M(48)>;
25 ahb-prescaler = <1>;
26 apb1-prescaler = <1>;
27 apb2-prescaler = <1>;
28 apb3-prescaler = <1>;
Dpll_hsi_160.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <40>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(160)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dpll_hsi_40.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <4>;
18 mul-n = <10>;
19 div-q = <2>;
20 div-r = <1>;
27 clock-frequency = <DT_FREQ_M(40)>;
28 ahb-prescaler = <1>;
29 apb1-prescaler = <1>;
30 apb2-prescaler = <1>;
31 apb3-prescaler = <1>;
Dhse_16.overlay4 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
25 clock-frequency = <DT_FREQ_M(16)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
Dpll_msis_ahb_2_40.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <4>;
26 div-r = <4>;
33 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
34 clock-frequency = <DT_FREQ_M(40)>;
35 apb1-prescaler = <1>;
[all …]
Dpll_msis_160.overlay4 * SPDX-License-Identifier: Apache-2.0
18 msi-range = <4>;
19 msi-pll-mode;
23 div-m = <1>;
24 mul-n = <80>;
25 div-q = <2>;
26 div-r = <2>;
33 clock-frequency = <DT_FREQ_M(160)>;
34 ahb-prescaler = <1>;
35 apb1-prescaler = <1>;
[all …]
Dpll_hsi_fracn_160.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <1>;
18 mul-n = <20>;
19 div-p = <2>;
20 div-q = <2>;
21 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(160)>;
30 ahb-prescaler = <1>;
31 apb1-prescaler = <1>;
32 apb2-prescaler = <1>;
[all …]
Dpll_hse_160.overlay4 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(16)>;
20 hse-bypass;
24 div-m = <4>;
25 mul-n = <40>;
26 div-q = <2>;
27 div-r = <1>;
34 clock-frequency = <DT_FREQ_M(160)>;
35 ahb-prescaler = <1>;
36 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dcsi4.overlay5 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(4)>;
20 ahb-prescaler = <1>;
21 apb1-prescaler = <1>;
22 apb2-prescaler = <1>;
23 apb3-prescaler = <1>;
Dhse24.overlay5 * SPDX-License-Identifier: Apache-2.0
20 clock-frequency = <DT_FREQ_M(24)>;
25 clock-frequency = <DT_FREQ_M(24)>;
26 ahb-prescaler = <1>;
27 apb1-prescaler = <1>;
28 apb2-prescaler = <1>;
29 apb3-prescaler = <1>;
Dpll_csi_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
18 div-m = <1>;
19 mul-n = <100>;
20 div-p = <2>;
21 div-q = <2>;
22 div-r = <2>;
29 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
30 clock-frequency = <DT_FREQ_M(100)>;
31 apb1-prescaler = <1>;
32 apb2-prescaler = <1>;
[all …]
Dhse25.overlay5 * SPDX-License-Identifier: Apache-2.0
19 clock-frequency = <DT_FREQ_M(25)>;
20 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
26 clock-frequency = <DT_FREQ_M(25)>;
27 ahb-prescaler = <1>;
28 apb1-prescaler = <1>;
29 apb2-prescaler = <1>;
30 apb3-prescaler = <1>;
Dpll_hse24_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(24)>;
19 div-m = <6>;
20 mul-n = <100>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
31 clock-frequency = <DT_FREQ_M(100)>;
32 apb1-prescaler = <1>;
[all …]
Dpll_hse25_ahb_2_100.overlay5 * SPDX-License-Identifier: Apache-2.0
14 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
15 clock-frequency = <DT_FREQ_M(25)>;
20 div-m = <4>;
21 mul-n = <64>;
22 div-p = <2>;
23 div-q = <2>;
24 div-r = <2>;
31 ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
32 clock-frequency = <DT_FREQ_M(100)>;
[all …]
Dpll_csi_100.overlay5 * SPDX-License-Identifier: Apache-2.0
17 /* Test another couple of M-div N-mul to obtain 100MHz from the CSI */
19 div-m = <1>;
20 mul-n = <50>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(100)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
Dpll_csi_240.overlay5 * SPDX-License-Identifier: Apache-2.0
17 /* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
19 div-m = <1>;
20 mul-n = <120>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(240)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
Dpll_hse24_100.overlay5 * SPDX-License-Identifier: Apache-2.0
20 clock-frequency = <DT_FREQ_M(24)>;
24 div-m = <6>;
25 mul-n = <50>;
26 div-p = <2>;
27 div-q = <2>;
28 div-r = <2>;
35 clock-frequency = <DT_FREQ_M(100)>;
36 ahb-prescaler = <1>;
37 apb1-prescaler = <1>;
[all …]
Dpll_hse24_240.overlay5 * SPDX-License-Identifier: Apache-2.0
20 clock-frequency = <DT_FREQ_M(24)>;
24 div-m = <2>;
25 mul-n = <40>;
26 div-p = <2>;
27 div-q = <2>;
28 div-r = <2>;
35 clock-frequency = <DT_FREQ_M(240)>;
36 ahb-prescaler = <1>;
37 apb1-prescaler = <1>;
[all …]
Dpll_hsi_240.overlay5 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
19 div-m = <4>;
20 mul-n = <30>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(240)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcm/
Dnpcm4.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 reg-io-width = <1>;
23 reg-io-width = <2>;
26 pcc: clock-controller@4000d000 {
27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
[all …]

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