Searched +full:ahb6 +full:- +full:prescaler (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcm-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm4.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
17 reg-io-width = <1>;
23 reg-io-width = <2>;
26 pcc: clock-controller@4000d000 {
27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | soc_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
37 /* Core clock prescaler */
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
54 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
67 * - OFMCLK > MAX_OFMCLK/2, XF_RANGE should be 1, else 0.
68 * - CORE_CLK > MAX_OFMCLK/2, AHB6DIV should be 1, else 0.
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_npcm.c | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
41 /* 0x008: HFCG Prescaler */
90 /* Core clock prescaler */
91 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
97 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
98 /* AHB6 clock divider*/
99 #define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
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