4  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/clock/npcm_clock.h>
41 	/* 0x008: HFCG Prescaler */
90 /* Core clock prescaler */
91 #define FPRED_VAL   (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
93 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
95 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
97 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
98 /* AHB6 clock divider*/
99 #define AHB6DIV_VAL (DT_PROP(DT_NODELABEL(pcc), ahb6_prescaler) - 1)
101 #define FIUDIV_VAL  (DT_PROP(DT_NODELABEL(pcc), fiu_prescaler) - 1)
103 #define I3CDIV_VAL  (DT_PROP(DT_NODELABEL(pcc), i3c_prescaler) - 1)
187 /* PMC multi-registers */
188 #define NPCM_PWDWN_CTL_OFFSET(n)     (((n) < 7) ? (0x07 + n) : (0x15 + (n - 7)))
193 #define DRV_CONFIG(dev) ((const struct npcm_pcc_config *)(dev)->config)
214 	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;  in npcm_clock_control_on()
219 		return -EINVAL;  in npcm_clock_control_on()
222 	/* Clear related PD (Power-Down) bit of module to turn on clock */  in npcm_clock_control_on()
223 	NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) &=  in npcm_clock_control_on()
224 		~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));  in npcm_clock_control_on()
233 	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;  in npcm_clock_control_off()
238 		return -EINVAL;  in npcm_clock_control_off()
241 	/* Set related PD (Power-Down) bit of module to turn off clock */  in npcm_clock_control_off()
242 	NPCM_PWDWN_CTL(pmc_base, NPCM_CLOCK_REG_OFFSET(priv->clock_id)) |=  in npcm_clock_control_off()
243 		~(BIT(NPCM_CLOCK_REG_BIT_OFFSET(priv->clock_id)));  in npcm_clock_control_off()
257 		return -EINVAL;  in npcm_clock_control_get_subsys_rate()
260 	switch (priv->bus) {  in npcm_clock_control_get_subsys_rate()
297 		return -EINVAL;  in npcm_clock_control_get_subsys_rate()
312 	struct cdcg_reg *const priv = (struct cdcg_reg *)(DRV_CONFIG(dev)->base_cdcg);  in npcm_clock_control_init()
325 		return -EINVAL;  in npcm_clock_control_init()
333 	if (priv->hfcgn != freq_p->hfcgn || priv->hfcgml != freq_p->hfcgml ||  in npcm_clock_control_init()
334 	    priv->hfcgmh != freq_p->hfcgmh) {  in npcm_clock_control_init()
339 		priv->hfcgn = freq_p->hfcgn;  in npcm_clock_control_init()
340 		priv->hfcgml = freq_p->hfcgml;  in npcm_clock_control_init()
341 		priv->hfcgmh = freq_p->hfcgmh;  in npcm_clock_control_init()
344 		priv->hfcgctrl |= BIT(NPCM_HFCGCTRL_LOAD);  in npcm_clock_control_init()
346 		while (sys_test_bit(priv->hfcgctrl, NPCM_HFCGCTRL_CLK_CHNG))  in npcm_clock_control_init()
351 	priv->hfcgp = (FPRED_VAL << 4) | AHB6DIV_VAL;  in npcm_clock_control_init()
352 	priv->hfcbcd = APB1DIV_VAL | (APB2DIV_VAL << 4);  in npcm_clock_control_init()
353 	priv->hfcbcd1 = (I3CDIV_VAL << 2) | FIUDIV_VAL;  in npcm_clock_control_init()
354 	priv->hfcbcd2 = APB3DIV_VAL;  in npcm_clock_control_init()