| /Zephyr-latest/dts/bindings/video/ |
| D | st,stm32-dcmi.yaml | 4 # SPDX-License-Identifier: Apache-2.0
14 pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
17 pinctrl-names = "default";
18 bus-width = <8>;
19 hsync-active = <0>;
20 vsync-active = <0>;
21 pixelclk-active = <1>;
22 capture-rate = <1>;
29 remote-endpoint = <&ov2640_ep_out>;
34 compatible: "st,stm32-dcmi"
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| /Zephyr-latest/dts/bindings/tcpc/ |
| D | nuvoton,numaker-tcpc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton NuMaker USB Type-C port controller
6 compatible: "nuvoton,numaker-tcpc"
8 include: [base.yaml, reset-device.yaml, pinctrl-device.yaml]
23 vconn-overcurrent-event-polarity:
28 - "low-active"
29 - "high-active"
31 vconn-discharge-polarity:
36 - "low-active"
37 - "high-active"
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| /Zephyr-latest/dts/bindings/adc/ |
| D | ti,ads131m02.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [adc-controller.yaml, spi-device.yaml]
11 "#io-channel-cells":
14 drdy-gpios:
15 type: phandle-array
18 GPIO for data ready, becomes active when a conversion result is ready.
19 By default, it is active low signal.
21 io-channel-cells:
22 - input
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| D | maxim,max1125x-base.yaml | 3 include: [adc-controller.yaml, spi-device.yaml]
6 "#io-channel-cells":
8 gpio0-enable:
11 gpio1-enable:
14 gpio0-direction:
17 gpio1-direction:
20 gpo0-enable:
23 gpo1-enable:
26 drdy-gpios:
27 type: phandle-array
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| D | ti,ads114s08.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [adc-controller.yaml, spi-device.yaml]
13 "#io-channel-cells":
16 reset-gpios:
17 type: phandle-array
20 drdy-gpios:
21 type: phandle-array
24 GPIO for data ready, becomes active when a conversion result is ready
26 start-sync-gpios:
27 type: phandle-array
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,fdc2x1x.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 sd-gpios:
12 type: phandle-array
14 The SD pin defaults to active high when consumed by the sensor.
18 intb-gpios:
19 type: phandle-array
21 The INTB pin defaults to active low when produced by the sensor.
28 Set to identify the sensor as FDC2114 or FDC2214 (4-channel version)
33 Set the Auto-Scan Mode.
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| D | avago,apds9253.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 int-gpios:
12 type: phandle-array
15 The interrupt pin of APDS9253 is open-drain, active low.
17 as pull-up, active low.
23 Select the rate interval (ms) for all comparator channel.
25 - <APDS9253_MEASUREMENT_RATE_2000MS>: 6
26 - <APDS9253_MEASUREMENT_RATE_1000MS>: 5
27 - <APDS9253_MEASUREMENT_RATE_500MS>: 4
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| D | ti,tmag5273.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Texas Instruments Low-Power Linear 3D Hall-Effect Sensor with an I2C interface.
17 #include <zephyr/dt-bindings/sensor/tmag5273.h>
27 include: [sensor-device.yaml, i2c-device.yaml]
30 operation-mode:
35 Sensor mode used if set to "active".
38 - 0 # TMAG5273_DT_OPER_MODE_CONTINUOUS (continuous)
39 - 1 # TMAG5273_DT_OPER_MODE_STANDBY (standby)
46 Magnet axis channel inputs.
49 - 0 # TMAG5273_DT_AXIS_NONE
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nordic,nrf-sw-pwm.yaml | 3 compatible: "nordic,nrf-sw-pwm"
5 include: [pwm-controller.yaml, base.yaml]
14 clock-prescaler:
25 channel-gpios:
26 type: phandle-array
36 sw_pwm: sw-pwm {
37 compatible = "nordic,nrf-sw-pwm";
39 channel-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>,
44 The above will assign P0.20 as the output for channel 0 and P1.12 as
45 the output for channel 1. Both outputs will be initially configured as
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| /Zephyr-latest/drivers/audio/ |
| D | dmic_mcux.c | 7 * SPDX-License-Identifier: Apache-2.0
57 * - DMIC DIVHFCLK is set to 0x0 (divide by 1) in dmic_mcux_get_osr()
58 * - DMIC PHY_HALF is set to 0x0 (standard sample rate) in dmic_mcux_get_osr()
63 /* Gets hardware channel index from logical channel */
70 /* This function assigns hardware channel "n" to the left channel, in dmic_mcux_hw_chan()
71 * and hardware channel "n+1" to the right channel. This choice is in dmic_mcux_hw_chan()
74 dmic_parse_channel_map(drv_data->chan_map_lo, in dmic_mcux_hw_chan()
75 drv_data->chan_map_hi, in dmic_mcux_hw_chan()
88 /* PDM channel 0 must always be enabled, as the RM states: in dmic_mcux_activate_channels()
91 * channel 0 FIFO, we still enable the channel so the clock is active. in dmic_mcux_activate_channels()
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| D | dmic_nrfx_pdm.c | 4 * SPDX-License-Identifier: Apache-2.0
34 volatile bool active; member
52 k_mem_slab_free(drv_data->mem_slab, drv_data->mem_slab_buffer); in free_buffer()
53 LOG_DBG("Freed buffer %p", drv_data->mem_slab_buffer); in free_buffer()
58 drv_data->stopping = true; in stop_pdm()
59 nrfx_pdm_stop(drv_data->pdm); in stop_pdm()
64 struct dmic_nrfx_pdm_drv_data *drv_data = dev->data; in event_handler()
65 const struct dmic_nrfx_pdm_drv_cfg *drv_cfg = dev->config; in event_handler()
69 if (evt->buffer_requested) { in event_handler()
73 ret = k_mem_slab_alloc(drv_data->mem_slab, &drv_data->mem_slab_buffer, K_NO_WAIT); in event_handler()
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| /Zephyr-latest/drivers/sensor/maxim/max30101/ |
| D | max30101.c | 4 * SPDX-License-Identifier: Apache-2.0
18 struct max30101_data *data = dev->data; in max30101_sample_fetch()
19 const struct max30101_config *config = dev->config; in max30101_sample_fetch()
26 /* Read all the active channels for one sample */ in max30101_sample_fetch()
27 num_bytes = data->num_channels * MAX30101_BYTES_PER_CHANNEL; in max30101_sample_fetch()
28 if (i2c_burst_read_dt(&config->i2c, MAX30101_REG_FIFO_DATA, buffer, in max30101_sample_fetch()
31 return -EIO; in max30101_sample_fetch()
36 /* Each channel is 18-bits */ in max30101_sample_fetch()
42 data->raw[fifo_chan++] = fifo_data; in max30101_sample_fetch()
52 struct max30101_data *data = dev->data; in max30101_channel_get()
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| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
20 individual channel) can be averaged and decimated on the chip by
54 Set to operate in heart rate only mode. The red LED channel is
55 active.
60 Set to operate in SpO2 mode. The red and IR LED channels are active.
63 bool "Multi-LED mode"
65 Set to operate in multi-LED mode. The green, red, and/or IR LED
66 channels are active.
75 Set the ADC's full-scale range.
87 pulse/conversion per active LED channel. In SpO2 mode, these means
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | dmic_regs_ace1x.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
25 /* Stream Channel Mapping Supported */
83 /* Digital Microphone PCM Stream y Channel Map
90 /* Lowest Channel */
93 /* Highest Channel */
100 /* Digital Microphone PCM Stream y Channel Count
107 /* Number of Channel Supported */
118 /* Left Channel SoundWire Bus Segment */
121 /* Right Channel SoundWire Bus Segment */
136 /* Set Power Active */
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | mipi_dsi.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DSI drivers
16 * @brief MIPI-DSI driver APIs
17 * @defgroup mipi_dsi_interface MIPI-DSI driver APIs
27 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
33 /** MIPI-DSI display timings. */
35 /** Horizontal active video. */
43 /** Vertical active video. */
54 * @name MIPI-DSI Device mode flags.
66 /** Enable hsync-end packets in vsync-pulse and v-porch area */
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| /Zephyr-latest/drivers/dai/intel/dmic/ |
| D | dmic_nhlt.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
19 /* Time-slot mappings */
31 /* i'th bit = 1 means that configuration for PDM channel # i is provided. */
37 /* Channel configuration, see PDM HW specification for details. */
88 * The index is 1-based, value of 0 means that FIR coefficients array fir_coeffs is provided
93 * reuse_fir_from_pdm to 1 (1-based index).
101 /* Array of FIR coefficients, channel A goes first, then channel B.
103 * Actual size of the array depends on the number of active taps of the FIR filter for
104 * channel A plus the number of active taps of the FIR filter for channel B (see FIR_CONFIG)
110 /* Tag indicating that FIRs are in a packed 24-bit format.
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | ti,tca954x-base.yaml | 2 # SPDX-License-Identifier: Apache-2.0
9 Each channel is represented by a separate devicetree child node.
10 The channel node can then be used as a standard i2c bus controller
18 #address-cells = <1>;
19 #size-cells = <0>;
20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
23 compatible: "ti,tca9546a-channel"
25 #address-cells = <1>;
26 #size-cells = <0>;
35 compatible: "ti,tca9546a-channel"
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| /Zephyr-latest/drivers/counter/ |
| D | counter_nxp_mrt.c | 4 * SPDX-License-Identifier: Apache-2.0
11 * initialization, interrupt handling, and any other module-wide tasks. The current implementation
34 (*(struct nxp_mrt_channel_data *const *const)dev->data)
36 /* Device config->data is an array of data pointers ordered by channel number,
37 * dev->data is a pointer to one of these pointers in that array,
38 * so the value of the dev->data - dev->config->data is the channel index
41 (((struct nxp_mrt_channel_data *const *)dev->data) - \
42 ((const struct nxp_mrt_config *)dev->config)->data)
44 /* Specific for each channel */
65 const struct nxp_mrt_config *config = dev->config; in nxp_mrt_stop()
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| /Zephyr-latest/dts/bindings/w1/ |
| D | maxim,ds2484.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: DS4284 Single-Channel 1-Wire Master
8 include: [i2c-device.yaml, w1-master.yaml]
11 slpz-gpios:
12 type: phandle-array
14 Enable sleep mode, only available on DS4284. Active low.
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| /Zephyr-latest/subsys/mgmt/osdp/ |
| D | Kconfig.pd | 4 # SPDX-License-Identifier: Apache-2.0
37 string "Secure Channel Base Key (SCBK)"
41 Channel Base Key. When this field is sent to "NONE", the PD is set to
43 channel with default SCBK. Once as secure channel is active with the
78 A 4-byte serial number for the PD.
86 - Bit 0-7 : build version number;
87 - Bit 8-15 : minor version number;
88 - Bit 16-23: major version number;
102 - 01: PD monitors and reports the state of the circuit without any
104 interpretation of contact state to active/inactive status.
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/ |
| D | dmic_regs.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
65 /* Common FIFO channels register (primary & secondary) (0000 - 0FFF)
66 * PDM Primary Channel
79 * (crossed out) 0010h LOCAL_TSC0 64-bit Wall Clock timestamp
80 * (crossed out) 0018h LOCAL_SAMPLE0 64-bit Sample Count
81 * 001Ch - 00FFh Reserved space for extensions
84 /* Offset to PDM Secondary Channel */
107 /* Control of the CIC filter plus voice channel (B) FIR decimation factor */
121 /* DC offset for left channel */
124 /* DC offset for right channel */
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/ |
| D | dmic_regs_ace3x.h | 3 * SPDX-License-Identifier: Apache-2.0
36 /* Set Power Active */
39 /* Current Power Active */
60 /* Digital Microphone PCM Stream y Channel Map
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| /Zephyr-latest/include/zephyr/drivers/dma/ |
| D | dma_mcux_lpc.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * LPC DMA engine channel hardware trigger attributes.
13 * in a dma_config structure to configure a channel for
18 * request line associated with this channel is used to pace DMA transfers.
23 * channel via INPUTMUX can be used to trigger a transfer
27 /* HW trigger polarity. When this bit is set, the trigger will be active
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| /Zephyr-latest/drivers/ps2/ |
| D | ps2_npcx_controller.c | 4 * SPDX-License-Identifier: Apache-2.0
21 #include <zephyr/dt-bindings/clock/npcx_clock.h>
30 * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to
39 * The max duration of a PS/2 clock is about 100 micro-seconds.
56 * (i.e. the bit position of CLK3-0 in the PS2_PSOSIG register)
71 ((struct ps2_reg *)((const struct ps2_npcx_ctrl_config *)(dev)->config)->base)
81 struct ps2_npcx_ctrl_data *const data = dev->data; in ps2_npcx_ctrl_configure()
84 LOG_ERR("unexpected channel ID: %d", channel_id); in ps2_npcx_ctrl_configure()
85 return -EINVAL; in ps2_npcx_ctrl_configure()
89 return -EINVAL; in ps2_npcx_ctrl_configure()
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| /Zephyr-latest/include/zephyr/drivers/timer/ |
| D | nrf_rtc_timer.h | 2 * Copyright (c) 2016-2020 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
24 * @param id Compare channel ID.
27 * channel. It can differ from the requested target time
37 /** @brief Allocate RTC compare channel.
39 * Channel 0 is used for the system clock.
41 * @retval Non-negative indicates allocated channel ID.
42 * @retval -ENOMEM if channel cannot be allocated.
46 /** @brief Free RTC compare channel.
48 * @param chan Previously allocated channel ID.
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