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/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
32 Selects the read mode:
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
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/Zephyr-latest/drivers/serial/
Duart_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
100 volatile uint32_t dll; /* Divisor latch LSB */ member
115 volatile uint32_t acr; /* Auto-baud Control */
124 volatile uint32_t rs485_ctrl; /* RS-485 control */
125 volatile uint32_t rs485_addr_match; /* RS-485 address match */
126 volatile uint32_t rs485_dly; /* RS-485 delay direction control
129 volatile uint32_t sync_ctrl; /* Synchronous mode control */
194 * we need to give the ISR a way to know all the devices that should be
/Zephyr-latest/boards/nxp/mr_canhubk3/
Dmr_canhubk3.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
14 #include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
17 model = "NXP MR-CANHUBK3";
25 zephyr,code-partition = &code_partition;
27 zephyr,shell-uart = &lpuart2;
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/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.c4 * SPDX-License-Identifier: Apache-2.0
14 * @retval 0 on success or -ETIMEDOUT error value on failure.
22 return -ETIMEDOUT; in cdns_nand_wait_idle()
28 * Set the row address for a NAND flash memory device using the Cadence NAND controller.
39 block_number = ((page_set) / (params->npages_per_block)); in row_address_set()
41 *local_row_address |= ROW_VAL_SET((params->page_size_bit) - 1, 0, in row_address_set()
42 ((page_set) % (params->npages_per_block))); in row_address_set()
44 ROW_VAL_SET((params->block_size_bit) - 1, (params->page_size_bit), block_number); in row_address_set()
45 *local_row_address |= ROW_VAL_SET((params->lun_size_bit) - 1, (params->block_size_bit), in row_address_set()
46 (block_number / params->nblocks_per_lun)); in row_address_set()
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Dflash_cadence_nand_ll.h4 * SPDX-License-Identifier: Apache-2.0
16 (k_sem_take(&(param_ptr->interrupt_sem_t), K_FOREVER)), ())
108 /* Mini controller DLL PHY controller register field offsets */
126 /* Async mode register field offsets */
208 /* DMA maximum burst size (0-127)*/
227 /*PIO Mode*/
297 #define DECR_CNT_ONE(x) (--x)
309 /* Flash address is a 32-bit address comprising of ROW ADDR. */
/Zephyr-latest/drivers/memc/
Dmemc_mcux_flexspi.c2 * Copyright 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
26 #warning "Enabling memc driver logging and XIP mode simultaneously can cause \
27 read-while-write hazards. This configuration is not recommended."
47 /* flexspi device data should be stored in RAM to avoid read-while-write hazards */
75 struct memc_flexspi_data *data = dev->data; in memc_flexspi_wait_bus_idle()
77 while (false == FLEXSPI_GetBusIdleStatus(data->base)) { in memc_flexspi_wait_bus_idle()
83 struct memc_flexspi_data *data = dev->data; in memc_flexspi_is_running_xip()
85 return data->xip; in memc_flexspi_is_running_xip()
92 struct memc_flexspi_data *data = dev->data; in memc_flexspi_update_clock()
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/Zephyr-latest/drivers/sdhc/
Dimx_usdhc.c4 * SPDX-License-Identifier: Apache-2.0
101 struct usdhc_data *data = dev->data; in transfer_complete_cb()
104 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
106 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
108 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
110 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
112 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
119 struct usdhc_data *data = dev->data; in sdio_interrupt_cb()
121 if (data->sdhc_cb) { in sdio_interrupt_cb()
122 data->sdhc_cb(dev, SDHC_INT_SDIO, data->sdhc_cb_user_data); in sdio_interrupt_cb()
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