Searched full:zynqmp (Results 1 – 25 of 32) sorted by relevance
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| /Zephyr-latest/drivers/fpga/ |
| D | Kconfig.zynqmp | 1 # FPGA ZYNQMP driver configuration options
7 bool "ZYNQMP fpga driver"
9 Enable ZYNQMP FPGA driver.
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| D | Kconfig | 33 source "drivers/fpga/Kconfig.zynqmp"
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | xlnx,ps-gpio.yaml | 7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
10 ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
24 ZynqMP (UltraScale) (comp. Ultrascale TRM, chap. 27, p. 769):
33 7000 and the ZynqMP are reserved or at least limited regarding their
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| D | xlnx,ps-gpio-bank.yaml | 7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
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| /Zephyr-latest/dts/arm/xilinx/ |
| D | zynqmp_rpu.dtsi | 7 #include <arm/xilinx/zynqmp.dtsi>
23 rpu0_ipi: zynqmp-ipi@ff310000 {
25 compatible = "xlnx,zynqmp-ipi-mailbox";
61 rpu1_ipi: zynqmp-ipi@ff320000 {
65 compatible = "xlnx,zynqmp-ipi-mailbox";
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| /Zephyr-latest/drivers/pinctrl/ |
| D | Kconfig.zynqmp | 5 bool "Xilinx ZynqMP pin controller driver"
9 Enable the Xilinx ZynqMP processor system MIO pin controller driver.
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| D | pinctrl_xlnx_zynqmp.c | 7 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynqmp.h>
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| D | Kconfig | 68 source "drivers/pinctrl/Kconfig.zynqmp"
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | xlnx,pinctrl-zynqmp.yaml | 5 Xilinx ZynqMP SoC pinctrl node. It allows configuration of pin assignments
10 compatible: "xlnx,pinctrl-zynqmp"
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| /Zephyr-latest/dts/bindings/fpga/ |
| D | xlnx,fpga.yaml | 4 description: Zynqmp FPGA driver
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| /Zephyr-latest/dts/bindings/timer/ |
| D | xlnx,ttcps.yaml | 1 description: Xilinx ZynqMP PS TTC timer
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| /Zephyr-latest/soc/xlnx/zynqmp/ |
| D | Kconfig.soc | 12 Xilinx ZynqMP RPU
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| D | pinctrl_soc.h | 29 * and the defines controling those are listed in `pinctrl-zynqmp.h`.
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.xlnx | 7 bool "Xilinx Zynq 7000/ZynqMP serial driver"
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| /Zephyr-latest/boards/enclustra/mercury_xu/ |
| D | mercury_xu-pinctrl.dtsi | 7 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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| D | mercury_xu.dts | 13 compatible = "xlnx,zynqmp";
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.xlnx_psttc | 12 This module implements a kernel device driver for the Xilinx ZynqMP
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| /Zephyr-latest/boards/qemu/cortex_r5/ |
| D | qemu_cortex_r5.dts | 13 compatible = "xlnx,zynqmp-qemu";
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| /Zephyr-latest/boards/amd/kv260_r5/ |
| D | kv260_r5.dts | 13 compatible = "xlnx,zynqmp-r5";
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| /Zephyr-latest/dts/bindings/ipm/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 8 compatible: "xlnx,zynqmp-ipi-mailbox"
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| /Zephyr-latest/drivers/ipm/ |
| D | Kconfig | 56 platforms such as ZynqMP Ultrascale+.
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| /Zephyr-latest/include/zephyr/dt-bindings/ethernet/ |
| D | xlnx_gem.h | 15 * According to the ZynqMP's gem.network_config register documentation (UG1087),
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| /Zephyr-latest/boards/qemu/cortex_r5/doc/ |
| D | index.rst | 7 (ZynqMP) platform.
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | pinctrl-zynqmp.h | 11 * The offset is defined at `pictrl_soc.h` for the ZynqMP platform
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| /Zephyr-latest/tests/kernel/sleep/src/ |
| D | main.c | 29 * The Xilinx QEMU, used to emulate the Xilinx ZynqMP platform, is particularly
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