Searched full:zynq (Results 1 – 25 of 33) sorted by relevance
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | xlnx,ps-gpio.yaml | 7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
9 This GPIO controller is contained in both the Xilinx Zynq-7000 and
18 Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
32 The controller is interrupt-capable. Certain pins both in the Zynq-
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| D | xlnx,ps-gpio-bank.yaml | 7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | xlnx,pinctrl-zynq.yaml | 5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
45 See the Xilinx Zynq-7000 SoC Technical Reference Manual (UG585) for further details on pin
48 compatible: "xlnx,pinctrl-zynq"
66 Xilinx Zynq 7000 SoC pin controller pin group
70 Xilinx Zynq 7000 SoC pin configuration node
175 macros are defined in pinctrl-zynq.h.
187 defined in pinctrl-zynq.h.
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| D | xlnx,pinctrl-zynqmp.yaml | 8 See Zynq UltraScale+ Devices Register Reference (UG1087) for details regarding
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| /Zephyr-latest/dts/bindings/arm/ |
| D | xlnx,zynq-ocm.yaml | 3 description: Xilinx Zynq OCM (On-Chip Memory)
5 compatible: "xlnx,zynq-ocm"
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| /Zephyr-latest/drivers/pinctrl/ |
| D | Kconfig.xlnx | 5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
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| /Zephyr-latest/boards/digilent/zybo/doc/ |
| D | index.rst | 9 The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital
10 circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the
51 The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be
56 with Xilinx Zynq-7000 series SoCs, see the following documentation:
74 export DEVICE_TREE="zynq-zybo"
83 the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot
109 Zynq> fatload mmc 0 0x0 zephyr.bin
111 Zynq> go 0x0
122 the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | pinctrl-zynq.h | 13 * Definitions for Xilinx Zynq-7000 pinctrl `power-source` devicetree property values. The value
27 * Definitions for Xilinx Zynq-7000 pinctrl `slew-rate` devicetree property values. The value
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| /Zephyr-latest/boards/qemu/cortex_r5/doc/ |
| D | index.rst | 6 This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
12 * Xilinx Zynq TTC (Cadence TTC)
13 * Xilinx Zynq UART
58 * Xilinx Zynq TTC driver does not support tickless mode operation.
103 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
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| /Zephyr-latest/include/zephyr/dt-bindings/ethernet/ |
| D | xlnx_gem.h | 17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
23 * on the UltraScale compared to the Zynq-7000.
25 * to both the UltraScale and the Zynq-7000.
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | Kconfig.soc | 6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
13 Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
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| D | Kconfig | 6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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| /Zephyr-latest/dts/arm/xilinx/ |
| D | zynq7000.dtsi | 16 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
22 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
175 compatible = "xlnx,zynq-slcr", "syscon";
180 compatible = "xlnx,pinctrl-zynq";
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| /Zephyr-latest/boards/digilent/zybo/ |
| D | zybo.dts | 16 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
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| D | zybo-pinctrl.dtsi | 7 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | Kconfig | 6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
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| D | Kconfig.soc | 6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
13 Enable support for the Xilinx Zynq-7000 (XC7Zxxx)
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| /Zephyr-latest/drivers/serial/ |
| D | Kconfig.xlnx | 7 bool "Xilinx Zynq 7000/ZynqMP serial driver"
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| /Zephyr-latest/boards/qemu/cortex_a9/ |
| D | Kconfig.defconfig | 2 # Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation
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| /Zephyr-latest/boards/amd/kv260_r5/doc/ |
| D | index.rst | 14 * Xilinx Zynq TTC (Cadence TTC)
15 * Xilinx Zynq UART
65 * Xilinx Zynq TTC driver does not support tickless mode operation.
152 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
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| /Zephyr-latest/dts/bindings/ipm/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xlnx_gem_priv.h | 26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
116 * Zynq-7000 TX clock configuration:
130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
578 * cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (UltraScale).
588 /* Dividers > 48 are only available in the Zynq-7000 */
679 * to clock sources, is specific to either the Zynq-7000 or the
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| /Zephyr-latest/drivers/timer/ |
| D | xlnx_psttc_timer_priv.h | 12 * Refer to the "Zynq UltraScale+ Device Technical Reference Manual" document
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_xlnx_ps_bank.h | 15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
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| /Zephyr-latest/boards/digilent/arty_a7/doc/ |
| D | index.rst | 11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
25 Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr.
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