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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
9 This GPIO controller is contained in both the Xilinx Zynq-7000 and
11 which can be mapped in the system design tools (MIO pins), or SoC-
18 Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
32 The controller is interrupt-capable. Certain pins both in the Zynq-
33 7000 and the ZynqMP are reserved or at least limited regarding their
36 compatible: "xlnx,ps-gpio"
Dxlnx,ps-gpio-bank.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
13 compatible: "xlnx,ps-gpio-bank"
15 include: [gpio-controller.yaml, base.yaml]
21 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
/Zephyr-latest/drivers/pinctrl/
DKconfig.xlnx2 # SPDX-License-Identifier: Apache-2.0
5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dpinctrl-zynq.h4 * SPDX-License-Identifier: Apache-2.0
13 * Definitions for Xilinx Zynq-7000 pinctrl `power-source` devicetree property values. The value
27 * Definitions for Xilinx Zynq-7000 pinctrl `slew-rate` devicetree property values. The value
/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h2 * Copyright (c) 2021-2022, Weidmueller Interface GmbH & Co. KG
3 * SPDX-License-Identifier: Apache-2.0
9 /* PHY auto-detection alias */
17 * documentation in UG1087 is likely wrong (copied directly from the Zynq-7000),
23 * on the UltraScale compared to the Zynq-7000.
24 * -> Contrary to earlier revisions of this driver, all dividers are available
25 * to both the UltraScale and the Zynq-7000.
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
[all …]
/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/
DKconfig.soc3 # SPDX-License-Identifier: Apache-2.0
6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
13 Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
14 SoC series (single core ARM Cortex-A9).
20 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
27 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
35 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic,
DKconfig3 # SPDX-License-Identifier: Apache-2.0
6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
/Zephyr-latest/dts/bindings/pinctrl/
Dxlnx,pinctrl-zynq.yaml2 # SPDX-License-Identifier: Apache-2.0
5 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
6 # https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
9 Xilinx Zynq-7000 SoC series pinctrl node. This node will define pin multiplexing and
18 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
21 pinctrl_uart1_default: uart1-default {
29 slew-rate = <IO_SPEED_SLOW>;
30 power-source = <IO_STANDARD_LVCMOS18>;
33 conf-rx {
35 bias-high-impedance;
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/Zephyr-latest/boards/digilent/zybo/doc/
Dindex.rst9 The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital
10 circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the
11 Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a
12 dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
14 .. figure:: zybo-0.jpg
28 +------------+------------+-------------------------------------+
31 | GICv1 | on-chip | ARM generic interrupt controller v1 |
32 +------------+------------+-------------------------------------+
33 | ARCH TIMER | on-chip | ARM architected timer |
34 +------------+------------+-------------------------------------+
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/Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
DKconfig.soc3 # SPDX-License-Identifier: Apache-2.0
6 # https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable
13 Enable support for the Xilinx Zynq-7000 (XC7Zxxx)
14 SoC series (dual core ARM Cortex-A9).
20 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
27 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
35 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic,
42 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
50 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
58 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic,
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/Zephyr-latest/drivers/serial/
DKconfig.xlnx4 # SPDX-License-Identifier: Apache-2.0
7 bool "Xilinx Zynq 7000/ZynqMP serial driver"
Duart_xlnx_ps.c1 /* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
6 * SPDX-License-Identifier: Apache-2.0
12 * @brief Xilinx Zynq Family Serial Driver
14 * This is the driver for the Xilinx Zynq family cadence serial device.
19 * - the following macro for the number of bytes between register addresses:
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
176 * of the UART are modified at run-time.
200 * of the UART are being modified at run-time.
222 * registers is described in the Zynq-7000 TRM, chapter 19.2.3 'Baud Rate
230 const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config; in set_baudrate()
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/Zephyr-latest/boards/qemu/cortex_a9/
DKconfig.defconfig2 # Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation
5 # SPDX-License-Identifier: Apache-2.0
/Zephyr-latest/boards/digilent/zybo/
Dzybo.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "zybo-pinctrl.dtsi"
16 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
18 #address-cells = <1>;
19 #size-cells = <1>;
24 zephyr,shell-uart = &uart1;
35 #address-cells = <1>;
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/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
86 * exhausted mid-frame
116 * Zynq-7000 TX clock configuration:
130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
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Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
[all …]
Dphy_xlnx_gem.c6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
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/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps_bank.h7 * SPDX-License-Identifier: Apache-2.0
15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
17 #define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
18 + ((uint32_t)dev_conf->bank_index * 0x8))
19 #define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
20 + ((uint32_t)dev_conf->bank_index * 0x8))
21 #define GPIO_XLNX_PS_BANK_DATA_REG ((dev_data->base + 0x40)\
22 + ((uint32_t)dev_conf->bank_index * 0x4))
23 #define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_data->base + 0x60)\
24 + ((uint32_t)dev_conf->bank_index * 0x4))
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/Zephyr-latest/boards/digilent/arty_a7/doc/
Dindex.rst9 The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
13 Each board is equipped with on-board JTAG for FPGA programming and debugging,
17 .. figure:: arty_a7-35.jpg
19 :alt: Digilent Arty A7-35
21 Digilent Arty A7-35 (Credit: Digilent Inc)
23 The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a
24 so-called soft processor to be instantiated within the FPGA in order to run
25 Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr.
27 ARM Cortex-M1/M3 DesignStart FPGA
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/Zephyr-latest/doc/build/dts/api/
Dapi.rst10 Some of these -- the ones beginning with ``DT_INST_`` -- require a special
19 .. _devicetree-generic-apis:
33 :ref:`devicetree-property-access` API.
45 .. doxygengroup:: devicetree-generic-id
47 .. _devicetree-property-access:
52 The following general-purpose macros can be used to access node properties.
53 There are special-purpose APIs for accessing the :ref:`devicetree-ranges-property`,
54 :ref:`devicetree-reg-property` and :ref:`devicetree-interrupts-property`.
59 .. doxygengroup:: devicetree-generic-prop
61 .. _devicetree-ranges-property:
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/Zephyr-latest/doc/releases/
Drelease-notes-3.6.rst12 * New :ref:`GNSS subsystem <gnss_api>` added, enabling geo-awareness in Zephyr applications.
13 * New API and drivers introduced for interfacing with :ref:`keyboard matrices <gpio-kbd>`.
16 * Integrated Trusted Firmware-M (TF-M) 2.0, including an update to Mbed TLS 3.5.2.
23 * Over 30 new supported boards, spanning all Zephyr-supported architectures.
37 * CVE-2023-5779 `Zephyr project bug tracker GHSA-7cmj-963q-jj47
38 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-7cmj-963q-jj47>`_
40 * CVE-2023-6249 `Zephyr project bug tracker GHSA-32f5-3p9h-2rqc
41 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-32f5-3p9h-2rqc>`_
43 * CVE-2023-6749 `Zephyr project bug tracker GHSA-757h-rw37-66hw
44 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-757h-rw37-66hw>`_
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Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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