Lines Matching +full:zynq +full:- +full:7000

7  * SPDX-License-Identifier: Apache-2.0
15  * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
17 #define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
18 	+ ((uint32_t)dev_conf->bank_index * 0x8))
19 #define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
20 	+ ((uint32_t)dev_conf->bank_index * 0x8))
21 #define GPIO_XLNX_PS_BANK_DATA_REG          ((dev_data->base + 0x40)\
22 	+ ((uint32_t)dev_conf->bank_index * 0x4))
23 #define GPIO_XLNX_PS_BANK_DATA_RO_REG       ((dev_data->base + 0x60)\
24 	+ ((uint32_t)dev_conf->bank_index * 0x4))
25 #define GPIO_XLNX_PS_BANK_DIRM_REG          ((dev_data->base + 0x204)\
26 	+ ((uint32_t)dev_conf->bank_index * 0x40))
27 #define GPIO_XLNX_PS_BANK_OEN_REG           ((dev_data->base + 0x208)\
28 	+ ((uint32_t)dev_conf->bank_index * 0x40))
29 #define GPIO_XLNX_PS_BANK_INT_MASK_REG      ((dev_data->base + 0x20C)\
30 	+ ((uint32_t)dev_conf->bank_index * 0x40))
31 #define GPIO_XLNX_PS_BANK_INT_EN_REG        ((dev_data->base + 0x210)\
32 	+ ((uint32_t)dev_conf->bank_index * 0x40))
33 #define GPIO_XLNX_PS_BANK_INT_DIS_REG       ((dev_data->base + 0x214)\
34 	+ ((uint32_t)dev_conf->bank_index * 0x40))
35 #define GPIO_XLNX_PS_BANK_INT_STAT_REG      ((dev_data->base + 0x218)\
36 	+ ((uint32_t)dev_conf->bank_index * 0x40))
37 #define GPIO_XLNX_PS_BANK_INT_TYPE_REG      ((dev_data->base + 0x21C)\
38 	+ ((uint32_t)dev_conf->bank_index * 0x40))
39 #define GPIO_XLNX_PS_BANK_INT_POLARITY_REG  ((dev_data->base + 0x220)\
40 	+ ((uint32_t)dev_conf->bank_index * 0x40))
41 #define GPIO_XLNX_PS_BANK_INT_ANY_REG       ((dev_data->base + 0x224)\
42 	+ ((uint32_t)dev_conf->bank_index * 0x40))
45  * @brief Run-time modifiable device data structure.
48  * which is modifiable at run-time, such as the configuration
64  * modified at run-time.