Searched full:xtal (Results 1 – 25 of 122) sorted by relevance
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| /Zephyr-latest/dts/bindings/clock/ |
| D | silabs,hfxo.yaml | 17 Mode of operation. Defaults to "xtal", expecting a crystal oscillator on XI and XO
20 default: "xtal"
21 enum: ["xtal", "extclk", "extclkpkdet"]
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| D | silabs,series2-lfxo.yaml | 25 Mode of operation. Defaults to "xtal", expecting a 32768 Hz crystal oscillator on XI and XO
28 default: "xtal"
29 enum: ["xtal", "bufextclk", "digextclk"]
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| D | espressif,esp32-rtc.yaml | 19 - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
20 ESP32_RTC_FAST_CLK_SRC_XTAL_D4 Main XTAL divided by 4 (ESP32/S2)
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| D | microchip,xec-pcr.yaml | 35 xtal-single-ended:
64 xtal-enable-delay-ms:
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| /Zephyr-latest/dts/bindings/rtc/ |
| D | ambiq,rtc.yaml | 15 default: "XTAL"
17 - "XTAL"
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| /Zephyr-latest/dts/bindings/phy/ |
| D | renesas,ra-usbphyc.yaml | 20 - "xtal"
22 Select clock source for PHY clock as XTAL or use internal clock
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| /Zephyr-latest/tests/drivers/clock_control/nrf_lf_clock_start/src/ |
| D | main.c | 51 bool xtal; in ZTEST() local
53 xtal = IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL) | in ZTEST()
57 if (xtal) { in ZTEST()
92 IS_ENABLED(CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL) ? "XTAL" in test_init()
117 * and XTAL has been started then LFSRCSTAT register content might be in get_lfclk_state()
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| /Zephyr-latest/dts/bindings/cpu/ |
| D | espressif,riscv.yaml | 26 xtal-freq:
29 description: Value of the external XTAL connected to ESP32. This is typically 40 MHz.
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| D | espressif,xtensa-lx6.yaml | 28 xtal-freq:
31 description: Value of the external XTAL connected to ESP32.
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| D | espressif,xtensa-lx7.yaml | 28 xtal-freq:
31 description: Value of the external XTAL connected to ESP32.
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| /Zephyr-latest/samples/drivers/clock_control_xec/src/ |
| D | main.c | 48 LOG_INF("32KHz clock source is XTAL"); in vbat_clock_regs()
50 LOG_INF("XTAL configured for single-ended using XTAL2 pin" in vbat_clock_regs()
53 LOG_INF("XTAL configured for parallel resonant crystal circuit on" in vbat_clock_regs()
90 LOG_INF("PLL 32K clock source is XTAL input(VTR)"); in print_pll_clock_src()
105 LOG_INF("Periph 32K clock source is XTAL(VTR) and XTAL(VBAT)"); in print_periph_clock_src()
109 LOG_INF("Periph 32K clock source is 32KHZ_PIN fallback to XTAL when VTR is off"); in print_periph_clock_src()
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| /Zephyr-latest/boards/renesas/ek_ra6m5/ |
| D | ek_ra6m5.dts | 94 &xtal {
106 clocks = <&xtal>;
123 phys-clock-src = "xtal";
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| /Zephyr-latest/drivers/clock_control/ |
| D | nrf_clock_calibration.c | 19 * periodically, calibration may include temperature monitoring, hf XTAL
23 * - process - calibration process which may consists of hf XTAL clock
115 /* Start actual HW calibration assuming that HFCLK XTAL is on. */
122 /* Start cycle by starting backoff timer and releasing HFCLK XTAL. */
161 /* Called when HFCLK XTAL is on. Schedules temperature measurement or triggers
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| /Zephyr-latest/boards/renesas/ek_ra6m3/ |
| D | ek_ra6m3.dts | 103 &xtal {
115 clocks = <&xtal>;
136 phys-clock-src = "xtal";
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| /Zephyr-latest/tests/boards/espressif/rtc_clk/ |
| D | testcase.yaml | 12 boards.esp32.rtc_clk.xtal:
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| /Zephyr-latest/boards/renesas/ek_ra6m1/ |
| D | ek_ra6m1.dts | 85 &xtal {
97 clocks = <&xtal>;
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| /Zephyr-latest/boards/renesas/ek_ra6m2/ |
| D | ek_ra6m2.dts | 81 &xtal {
93 clocks = <&xtal>;
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| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | ssp.h | 80 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
81 * Even in the case of M/N, the actual clock source can be XTAL,
94 MN_BCLK_SOURCE_XTAL, /**< port is using XTAL directly */
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| /Zephyr-latest/soc/nuvoton/numicro/m48x/ |
| D | soc.c | 18 /* Enable HXT clock (external XTAL 12MHz) */ in soc_reset_hook()
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| /Zephyr-latest/soc/atmel/sam/common/ |
| D | soc_pmc.h | 259 /* Wait the main Xtal to stabilize */ in soc_pmc_osc_enable_main_xtal()
314 * @param bypass select bypass or xtal
321 /* Enable Main Xtal oscillator */ in soc_pmc_switch_mainck_to_xtal()
333 /* Wait for the Xtal to stabilize */ in soc_pmc_switch_mainck_to_xtal()
344 * @param bypass select bypass or xtal
348 /* Disable xtal oscillator */ in soc_pmc_osc_disable_xtal()
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| /Zephyr-latest/boards/renesas/ek_ra4m2/ |
| D | ek_ra4m2.dts | 62 &xtal {
74 clocks = <&xtal>;
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| /Zephyr-latest/boards/renesas/ek_ra4m3/ |
| D | ek_ra4m3.dts | 62 &xtal {
74 clocks = <&xtal>;
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| /Zephyr-latest/samples/drivers/clock_control_xec/boards/ |
| D | mec1501modular_assy6885.overlay | 15 xtal-single-ended;
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| D | mec15xxevb_assy6853.overlay | 15 xtal-single-ended;
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| D | mec172xevb_assy6906.overlay | 15 xtal-single-ended;
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