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/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_tree_config.h46 /* TRACECLK */
48 #if DT_NUM_CLOCKS(DT_NODELABEL(traceclk)) == 0
52 /* TRACECLK can be clocked from SYSCLK */
54 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(sysclk)) \
56 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcodpllrt)) \
59 DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), \
65 /* TRACECLK can be clocked from HCLK */
67 (DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hclk)) \
69 : DT_SAME_NODE(DT_CLOCKS_CTLR(DT_NODELABEL(traceclk)), DT_NODELABEL(hfrcoem23)) \
74 #error "Invalid clock source selection for TRACECLK"
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/Zephyr-latest/dts/bindings/gpio/
Dnordic-thingy53-edge-connector.yaml24 P19 P0.12/TRACECLK
/Zephyr-latest/dts/arm/silabs/
Defr32bg2x.dtsi54 traceclk: traceclk { label
Defr32mg21.dtsi54 traceclk: traceclk { label
Defr32mg24.dtsi64 traceclk: traceclk { label
Defr32xg23.dtsi64 traceclk: traceclk { label
/Zephyr-latest/boards/nordic/thingy53/
Dthingy53_nrf5340_cpunet.dts83 <19 0 &gpio0 12 0>; /* P19, P0.12/TRACECLK */
Dthingy53_nrf5340_common.dtsi77 <19 0 &gpio0 12 0>; /* P19, P0.12/TRACECLK */
/Zephyr-latest/boards/segger/trb_stm32f407/doc/
Dindex.rst73 | 11 | 5V-Supply | 12 | TRACECLK |
/Zephyr-latest/boards/aconno/acn52832/doc/
Dindex.rst99 | 30 | | P0.20/TRACECLK | |
/Zephyr-latest/boards/pine64/pinetime_devkit0/doc/
Dindex.rst74 | P0.20/TRACECLK | | |
/Zephyr-latest/boards/ezurio/bl652_dvk/doc/
Dbl652_dvk.rst176 | 2 | D9 | P0.20 / TRACECLK |
/Zephyr-latest/boards/u-blox/ubx_bmd300eval/doc/
Dindex.rst314 | 9 | D9 | P0.20/TRACECLK |
/Zephyr-latest/boards/arm/mps2/doc/
Dmps2_an521.rst353 - TRACECLK : 20MHz
/Zephyr-latest/boards/nordic/nrf52dk/doc/
Dindex.rst311 | 2 | D9 | P0.20 / TRACECLK |
/Zephyr-latest/boards/nxp/vmu_rt1170/doc/
Dindex.rst243 | GPIO_DISP_B2_06 | ARM_TRACE_CLK | TRACECLK |