| /Zephyr-Core-2.7.6/dts/arm/infineon/ |
| D | xmc4xxx.dtsi | 38 sysclk: system-clock { label
47 clocks = <&sysclk>;
53 clocks = <&sysclk>;
59 clocks = <&sysclk>;
65 clocks = <&sysclk>;
71 clocks = <&sysclk>;
77 clocks = <&sysclk>;
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| /Zephyr-Core-2.7.6/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 6 This node is in charge of system clock ('SYSCLK') source selection and controlling
13 As part of this node configuration, SYSCLK frequency should also be defined, using
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(80)>; /* SYSCLK runs at 80MHz */
63 lower than SYSCLK frequency (actual core frequency).
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| D | st,stm32h7-rcc.yaml | 6 This node is in charge of system clock ('SYSCLK') source selection and
13 As part of this node configuration, SYSCLK frequency should also be defined, using
19 clocks = <&pll>; /* Set pll as SYSCLK source */
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
66 lower than SYSCLK frequency (actual core frequency).
|
| D | st,stm32f100-pll-clock.yaml | 14 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
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| D | st,stm32f1-pll-clock.yaml | 13 f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)
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| D | st,stm32f0-pll-clock.yaml | 14 f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
|
| /Zephyr-Core-2.7.6/boards/arm/mps2_an521/ |
| D | mps2_an521-common.dtsi | 7 sysclk: system-clock { label
87 clocks = <&sysclk>;
96 clocks = <&sysclk>;
106 clocks = <&sysclk>;
116 clocks = <&sysclk>;
126 clocks = <&sysclk>;
136 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/boards/arm/mps3_an547/ |
| D | mps3_an547-common.dtsi | 7 sysclk: system-clock { label
138 clocks = <&sysclk>;
148 clocks = <&sysclk>;
158 clocks = <&sysclk>;
168 clocks = <&sysclk>;
178 clocks = <&sysclk>;
189 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/drivers/clock_control/ |
| D | clock_stm32_ll_h7.c | 105 /* All h7 SoC with maximum 480MHz SYSCLK */
111 /* All h7 SoC with maximum 550MHz SYSCLK */
116 /* Default: All h7 SoC with maximum 280MHz SYSCLK */
123 #error "SYSCLK frequency is too high!"
152 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
185 uint32_t sysclk = 0; in get_hclk_frequency() local
209 sysclk = HSI_VALUE/hsidiv; in get_hclk_frequency()
212 sysclk = CSI_VALUE; in get_hclk_frequency()
215 sysclk = HSE_VALUE; in get_hclk_frequency()
218 sysclk = PLLP_FREQ(get_pllsrc_frequency(), in get_hclk_frequency()
[all …]
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| D | Kconfig.stm32 | 60 Use HSE as source of SYSCLK
65 Use HSI as source of SYSCLK
71 Use MSI as source of SYSCLK
76 Use PLL as source of SYSCLK
82 Use CSI as source of SYSCLK
284 bool "SYSCLK"
287 Use SYSCLK as source of MCO2
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| D | clock_stm32_ll_u5.c | 37 * lower than SYSCLK frequency (actual core frequency).
185 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler) in stm32_clock_control_get_subsys_rate()
277 * Configure PLL as source of SYSCLK
288 * (Switching to HSI makes sure we have a SYSCLK source in in config_src_sysclk_pll()
294 * use when the SYSCLK source is the PLL, not HSI. in config_src_sysclk_pll()
407 * Configure HSE as source of SYSCLK
473 * Configure MSI as source of SYSCLK
536 * Configure HSI as source of SYSCLK
552 /* HSI used as SYSCLK, set latency to 0 */ in config_src_sysclk_hsi()
575 /* Configure PLL as source of SYSCLK */ in stm32_clock_control_init()
[all …]
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| /Zephyr-Core-2.7.6/boards/arm/v2m_beetle/ |
| D | v2m_beetle.dts | 44 sysclk: system-clock { label
76 clocks = <&sysclk>;
85 clocks = <&sysclk>;
92 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/boards/arm/mps2_an385/ |
| D | mps2_an385.dts | 73 sysclk: system-clock { label
106 clocks = <&sysclk>;
116 clocks = <&sysclk>;
126 clocks = <&sysclk>;
136 clocks = <&sysclk>;
143 clocks = <&sysclk>;
153 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/dts/arm/ti/ |
| D | msp432p4xx.dtsi | 24 sysclk: system-clock { label
35 clocks = <&sysclk>;
|
| D | lm3s6965.dtsi | 22 sysclk: system-clock { label
46 clocks = <&sysclk>;
55 clocks = <&sysclk>;
64 clocks = <&sysclk>;
|
| D | cc32xx.dtsi | 52 sysclk: system-clock { label
63 clocks = <&sysclk>;
72 clocks = <&sysclk>;
79 clocks = <&sysclk>;
|
| D | cc13x2_cc26x2.dtsi | 41 sysclk: system-clock { label
75 clocks = <&sysclk>;
84 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/boards/arm/v2m_musca_b1/ |
| D | v2m_musca_b1-common.dtsi | 33 clocks = <&sysclk>;
43 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/boards/arm/v2m_musca_s1/ |
| D | v2m_musca_s1-common.dtsi | 33 clocks = <&sysclk>;
43 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/dts/arc/ |
| D | emsk.dtsi | 31 sysclk: system-clock { label
145 clocks = <&sysclk>;
157 clocks = <&sysclk>;
|
| D | arc_iot.dtsi | 51 sysclk: system-clock { label
234 clocks = <&sysclk>;
247 clocks = <&sysclk>;
260 clocks = <&sysclk>;
|
| /Zephyr-Core-2.7.6/dts/arm/nxp/ |
| D | nxp_rt1020.dtsi | 9 &sysclk {
|
| D | nxp_rt1015.dtsi | 9 &sysclk {
|
| D | nxp_rt1024.dtsi | 9 &sysclk {
|
| /Zephyr-Core-2.7.6/drivers/i2c/ |
| D | i2c_ll_stm32.c | 40 * HSI and SYSCLK, not APB1. We force clock variable to in i2c_stm32_runtime_configure()
41 * SYSCLK frequency. in i2c_stm32_runtime_configure()
218 * HSI and SYSCLK, not APB1. We force I2C clock source to SYSCLK. in i2c_stm32_init()
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