Searched full:siul2 (Results 1 – 16 of 16) sorted by relevance
| /Zephyr-Core-3.7.0/include/zephyr/drivers/interrupt_controller/ |
| D | intc_eirq_nxp_s32.h | 15 /** NXP SIUL2 EIRQ callback */
19 * @brief NXP SIUL2 EIRQ pin activation type
33 * @param dev SIUL2 EIRQ device
41 * @param dev SIUL2 EIRQ device
56 * @param dev SIUL2 EIRQ device
66 * @param dev SIUL2 EIRQ device
74 * @param dev SIUL2 EIRQ device
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| /Zephyr-Core-3.7.0/dts/bindings/interrupt-controller/ |
| D | nxp,s32-siul2-eirq.yaml | 5 description: NXP S32 SIUL2 External Interrupts Request controller
7 compatible: "nxp,s32-siul2-eirq"
26 clock to SIUL2, which is the peripheral clock counter in the SIUL2.
35 NXP S32 SIUL2 External Interrupt configuration. Specific filter requirements
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| /Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
| D | intc_eirq_nxp_s32.c | 16 /* SIUL2 External Interrupt Controller registers (offsets from DISR0) */
17 /* SIUL2 DMA/Interrupt Status Flag */
19 /* SIUL2 DMA/Interrupt Request Enable */
21 /* SIUL2 DMA/Interrupt Request Select */
23 /* SIUL2 Interrupt Rising-Edge Event Enable */
25 /* SIUL2 Interrupt Falling-Edge Event Enable */
27 /* SIUL2 Interrupt Filter Enable */
29 /* SIUL2 Interrupt Filter Maximum Counter Register */
33 /* SIUL2 Interrupt Filter Clock Prescaler Register */
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| D | Kconfig.nxp_s32 | 21 Number of SIUL2 external interrupts per controller. This is a SoC
28 Number of SIUL2 external interrupts grouped into a single core
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| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/ |
| D | nxp-s32-pinctrl.h | 19 * - 25..27: MSCR SIUL2 instance index (0..7)
20 * - 28..30: IMCR SIUL2 instance index (0..7)
75 * @param mscr_siul2_idx MSCR SIUL2 instance index
76 * @param imcr_siul2_idx IMCR SIUL2 instance index
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| /Zephyr-Core-3.7.0/drivers/pinctrl/ |
| D | pinctrl_nxp_s32.c | 10 /* SIUL2 Multiplexed Signal Configuration Register */
12 /* SIUL2 Input Multiplexed Signal Configuration Register */
19 * Utility macro that expands to the SIUL2 base address if it exists or zero.
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| /Zephyr-Core-3.7.0/dts/bindings/gpio/ |
| D | nxp,s32-gpio.yaml | 8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
10 SIUL2 EIRQ interrupt controller.
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| /Zephyr-Core-3.7.0/soc/nxp/s32/s32k3/ |
| D | pinctrl_soc.h | 15 /* SIUL2 Multiplexed Signal Configuration */
38 /* SIUL2 Input Multiplexed Signal Configuration */
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| /Zephyr-Core-3.7.0/soc/nxp/s32/s32ze/ |
| D | pinctrl_soc.h | 15 /* SIUL2 Multiplexed Signal Configuration */
40 /* SIUL2 Input Multiplexed Signal Configuration */
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| /Zephyr-Core-3.7.0/dts/arm/nxp/ |
| D | nxp_s32z27x_r52.dtsi | 213 siul2_0: siul2@40520000 {
219 compatible = "nxp,s32-siul2-eirq";
264 siul2_1: siul2@40d20000 {
270 compatible = "nxp,s32-siul2-eirq";
335 siul2_3: siul2@41d20000 {
339 siul2_4: siul2@42520000 {
345 compatible = "nxp,s32-siul2-eirq";
412 siul2_5: siul2@42d20000 {
418 compatible = "nxp,s32-siul2-eirq";
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| D | nxp_s32k344_m7.dtsi | 85 siul2_0: siul2@40290000 {
91 compatible = "nxp,s32-siul2-eirq";
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| /Zephyr-Core-3.7.0/soc/nxp/s32/common/ |
| D | siul2_pinctrl.h | 21 /** @brief Type for NXP SIUL2 pin configuration. */
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| /Zephyr-Core-3.7.0/drivers/gpio/ |
| D | gpio_nxp_s32.c | 25 /* SIUL2 Multiplexed Signal Configuration Register (offset from port base) */
27 /* SIUL2 Parallel GPIO Pad Data Out (offset from gpio base) */
29 /* SIUL2 Parallel GPIO Pad Data In */
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| /Zephyr-Core-3.7.0/boards/nxp/mr_canhubk3/doc/ |
| D | index.rst | 48 SIUL2 on-chip | pinctrl
78 to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC.
79 By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller,
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| /Zephyr-Core-3.7.0/boards/nxp/s32z2xxdc2/doc/ |
| D | index.rst | 44 | SIUL2 | on-chip | pinctrl |
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| /Zephyr-Core-3.7.0/doc/releases/ |
| D | release-notes-3.3.rst | 757 * Added NXP S32 GPIO (SIUL2) driver
797 * Added NXP S32 External Interrupt Controller (SIUL2) driver.
832 * Added NXP S32 SIUL2 driver
1376 - :dtcompatible:`nxp,s32-siul2-eirq`
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