1# Copyright 2022-2024 NXP
2#
3# SPDX-License-Identifier: Apache-2.0
4
5description: NXP S32 SIUL2 External Interrupts Request controller
6
7compatible: "nxp,s32-siul2-eirq"
8
9include: [interrupt-controller.yaml, pinctrl-device.yaml, base.yaml]
10
11properties:
12  reg:
13    required: true
14
15  pinctrl-0:
16    required: true
17
18  pinctrl-names:
19    required: true
20
21  filter-prescaler:
22    type: int
23    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
24    description: |
25      Interrupt filter clock prescaler. The prescaler is applied to the input
26      clock to SIUL2, which is the peripheral clock counter in the SIUL2.
27      The prescaled filter clock period is:
28        TIRC * (IFCP + 1)
29      where:
30        * TIRC is the internal oscillator period.
31        * IFCP is 0 to 15.
32
33child-binding:
34  description: |
35    NXP S32 SIUL2 External Interrupt configuration. Specific filter requirements
36    for each interrupt can be specified by adding a child node to the interrupt
37    controller, labeled `irq_<interrupt-number>`. For example:
38
39      irq_0: irq_0 {
40          max-filter-counter = <5>;
41      };
42
43    This will enable a digital filter counter on the corresponding interrupt
44    pads to filter out glitches on the inputs. The digital filter will be
45    disabled for interrupt lines without specified configuration node.
46
47  properties:
48    max-filter-counter:
49      type: int
50      required: true
51      enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
52      description: |
53        Maximum Interrupt Filter Counter setting. This value configures the
54        filter counter associated with the digital glitch filter.
55        A value of 0 to 2, sets the filter as an all pass filter.
56        A value of 3 to 15, sets the filter period to (TCK * MAXCNT + n * TCK),
57        where:
58          * n can be in the range 0 to 4, and accounts for the uncertainty
59            factor in filter period calculation.
60          * TCK is the prescaled filter clock period.
61
62interrupt-cells:
63  - gpio-pin
64  - eirq-line
65