| /Zephyr-latest/drivers/reset/ |
| D | Kconfig | 1 # Reset Controller driver configuration options
7 # Reset Controller options
9 menuconfig RESET config
10 bool "Reset Controller drivers"
12 Reset Controller drivers. Reset node represents a region containing
13 information about reset controller device. The typical use-case is
14 for some other node's drivers to acquire a reference to the reset
15 controller node together with some reset information.
17 if RESET
20 int "Reset Controller driver init priority"
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| /Zephyr-latest/dts/bindings/power/ |
| D | nxp,s32-mc-rgm.yaml | 4 description: NXP S32 Module Reset Generation (MC_RGM)
14 func-reset-threshold:
19 Functional Reset Escalation threshold.
20 If the value of this property is 0, the Functional reset escalation
22 resets that causes a Destructive reset, if the FRET register isn't
24 Default to maximum threshold (hardware reset value).
26 dest-reset-threshold:
31 Destructive Reset Escalation threshold.
32 If the value of this property is 0, the Destructive reset escalation
34 resets which keeps the chip in the reset state until the next power-on
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | reset.h | 3 * @brief Reset Controller Devicetree macro public API header file.
20 * @defgroup devicetree-reset-controller Devicetree Reset Controller API
31 * reset1: reset-controller@... { ... };
33 * reset2: reset-controller@... { ... };
46 * @return the node identifier for the reset controller referenced at
56 * @return a node identifier for the reset controller at index 0
69 * reset1: reset-controller@... { ... };
71 * reset2: reset-controller@... { ... };
75 * reset-names = "alpha", "beta";
85 * as defined by the node's reset-names property
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | reset.h | 9 * @brief Public Reset Controller driver APIs
16 * @brief Reset Controller Interface
17 * @defgroup reset_controller_interface Reset Controller Interface
33 /** Reset controller device configuration. */
35 /** Reset controller device. */
37 /** Reset line. */
45 * devicetree node identifier, a property specifying a Reset Controller and an index.
50 * resets = <&reset 10>;
58 * // .dev = DEVICE_DT_GET(DT_NODELABEL(reset)),
62 * The 'reset' field must still be checked for readiness, e.g. using
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| D | hwinfo.h | 36 * @name Reset cause flags
42 /** Software reset */
46 /** Power-on reset (POR) */
64 /** Hardware reset */
66 /** User reset */
68 /** Temperature reset */
115 * @brief Retrieve cause of device reset.
117 * @param cause OR'd @ref reset_cause "reset cause" flags
119 * This routine retrieves the flags that indicate why the device was reset.
121 * On some platforms the reset cause flags accumulate between successive resets
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| /Zephyr-latest/dts/bindings/reset/ |
| D | gd,gd32-rctl.yaml | 5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
9 To specify the reset line in a peripheral, the standard resets property needs
19 Predefined RCU reset cells are available in
20 include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
25 include: [reset-controller.yaml, base.yaml]
28 "#reset-cells":
31 reset-cells:
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| D | st,stm32-rcc-rctl.yaml | 5 STM32 Reset and Clock Control (RCC) node.
6 This node is in charge of reset control for AHB (Advanced High Performance)
9 To specify the reset line in a peripheral, the standard resets property needs
19 RCC reset cells are available in
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
34 deassert reset.
36 reset-cells:
|
| D | raspberrypi,pico-reset.yaml | 4 description: Raspberry Pi Pico Reset Controller
6 compatible: "raspberrypi,pico-reset"
8 include: [base.yaml, reset-controller.yaml]
15 description: The width of the reset registers in bytes. Default is 4 bytes.
18 description: Set if reset is active low. Default is 0, which means active-high.
19 "#reset-cells":
22 reset-cells:
|
| D | intel,socfpga-reset.yaml | 4 description: Intel SoC FPGA Reset Controller
6 compatible: "intel,socfpga-reset"
8 include: [base.yaml, reset-controller.yaml]
15 description: Add this property in dts node if the reset line is active_low, otherwise do not
17 "#reset-cells":
20 reset-cells:
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| D | nxp,lpc-syscon-reset.yaml | 4 description: LPC SYSCON Peripheral reset controller
6 compatible: "nxp,lpc-syscon-reset"
8 include: [reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
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| D | aspeed,ast10x0-reset.yaml | 4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
8 include: [base.yaml, reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | reset.rst | 3 Reset Controller
9 Reset controllers are units that control the reset signals to multiple
10 peripherals. The reset controller API allows peripheral drivers to request
11 control over their reset input signals, including the ability to assert,
12 deassert and toggle those signals. Also, the reset status of the reset input
16 in most cases we want to toggle the reset signals.
|
| /Zephyr-latest/samples/drivers/espi/boards/ |
| D | mec172xevb_assy6906.overlay | 24 reset-state = "1";
25 reset-source = "ESPI_RESET";
30 reset-state = "1";
31 reset-source = "ESPI_RESET";
36 reset-state = "1";
37 reset-source = "ESPI_RESET";
42 reset-state = "1";
43 reset-source = "ESPI_RESET";
|
| D | mec172xmodular_assy6930.overlay | 21 reset-state = "1";
22 reset-source = "ESPI_RESET";
27 reset-state = "1";
28 reset-source = "ESPI_RESET";
33 reset-state = "1";
34 reset-source = "ESPI_RESET";
39 reset-state = "1";
40 reset-source = "ESPI_RESET";
|
| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | nxp,lcdic.yaml | 27 reset-gpios:
30 Reset GPIO pin. The controller will set this pin to logic high to reset
31 the display. If not provided, the LCDIC module's reset pin will be used
32 to reset attached displays.
40 WRX signal. Default is IP reset value. Only valid in 8080 mode.
48 WRX signal. Default is IP reset value. Only valid in 8080 mode.
54 Ratio for timer0, used for setting timer0 period (which is used for reset
57 Default is IP reset value
66 Default is IP reset value
|
| /Zephyr-latest/dts/bindings/test/ |
| D | vnd,reset.yaml | 4 description: Test Reset Controller
6 compatible: "vnd,reset"
8 include: [base.yaml, reset-controller.yaml]
14 "#reset-cells":
17 reset-cells:
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| /Zephyr-latest/dts/bindings/bluetooth/ |
| D | renesas,bt-hci-da1453x.yaml | 6 controller, allowing control of the GPIO used to reset the DA1453x.
13 reset-gpios:
16 This gpio is used to reset the DA1453x.
18 reset-assert-duration-ms:
21 Minimum duration to activate the reset-gpios pin.
28 Minimum time to wait for the DA1453x to boot following a hardware reset.
|
| /Zephyr-latest/soc/nxp/s32/common/ |
| D | mc_rgm.c | 16 /* Functional / External Reset Status Register */
20 /* Functional Event Reset Disable Register */
22 /* Functional Bidirectional Reset Enable Register */
24 /* Functional Reset Escalation Counter Register */
28 /* Functional Reset Escalation Threshold Register */
32 /* Destructive Reset Escalation Threshold Register */
36 /* External Reset Control Register */
40 /* Reset During Standby Status Register */
46 /* Functional Reset Entry Timeout Control Register */
94 /* All functional reset sources generate a reset event */ in mc_rgm_init()
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| /Zephyr-latest/drivers/watchdog/ |
| D | Kconfig.smartbond | 15 bool "NMI pre-reset interrupt enable"
21 reset at <= -16. Timer can be frozen/resumed using
25 reset at value 0 and can not be frozen by Software.
27 only be reset with a WDOG (SYS) reset or SW reset.
|
| /Zephyr-latest/dts/bindings/gpio/ |
| D | nxp,pcal64xxa-base.yaml | 13 reset-gpios:
16 GPIO connected to the controller RESET pin. This pin is active-low.
18 no-auto-reset:
21 This flag disables the automatic reset, which allows the implementation
24 port expander the manual reset is triggered via the exposed reset
|
| /Zephyr-latest/boards/st/stm32h573i_dk/support/ |
| D | openocd.cfg | 10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
|
| /Zephyr-latest/boards/st/nucleo_h503rb/support/ |
| D | openocd.cfg | 10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
|
| /Zephyr-latest/boards/st/nucleo_h533re/support/ |
| D | openocd.cfg | 10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
|
| /Zephyr-latest/boards/st/nucleo_h563zi/support/ |
| D | openocd.cfg | 10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
|
| /Zephyr-latest/dts/bindings/espi/ |
| D | microchip,xec-espi-vw-routing.yaml | 28 reset-state:
31 Optional default virtual wire state on reset (0 or 1).
38 reset-source:
41 Optional reset source in addition to chip reset.
43 and 3 is ESPI Platform Reset. If this property is not
44 present the hardware default is used. Note: reset source
|
