Searched full:qspic2 (Results 1 – 4 of 4) sorted by relevance
74 reg = QSPIC2->QSPIC2_CTRLMODE_REG; in memc_automode_configure()82 QSPIC2->QSPIC2_CTRLMODE_REG = reg; in memc_automode_configure()84 reg = QSPIC2->QSPIC2_BURSTCMDA_REG; in memc_automode_configure()101 QSPIC2->QSPIC2_BURSTCMDA_REG = reg; in memc_automode_configure()103 reg = QSPIC2->QSPIC2_BURSTCMDB_REG; in memc_automode_configure()111 QSPIC2->QSPIC2_BURSTCMDB_REG = reg; in memc_automode_configure()113 reg = QSPIC2->QSPIC2_AWRITECMD_REG; in memc_automode_configure()122 QSPIC2->QSPIC2_AWRITECMD_REG = reg; in memc_automode_configure()150 qspic_ctrlmode_reg = QSPIC2->QSPIC2_CTRLMODE_REG; in memc_smartbond_init()154 QSPIC2->QSPIC2_CTRLMODE_REG = qspic_ctrlmode_reg; in memc_smartbond_init()[all …]
128 Clock divider for QSPIC2 controller. The clock path of136 consideration by QSPIC2 so that it can split a burst read/write
569 /* Make sure QSPIC2 is enabled */ in smartbond_clocks_init()620 /* Make sure QSPIC2 is enabled */ in smartbond_clocks_pm_action()
397 memc: qspic2@34000000 {
