Searched full:port0 (Results 1 – 24 of 24) sorted by relevance
| /Zephyr-latest/dts/bindings/gpio/ |
| D | awinic,aw9523b-gpio.yaml | 25 port0-push-pull:
28 Configure Port0 to Push-Pull mode.
29 Port0 is worked in Open-Drain mode by default.
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| D | ene,kb1200-gpio.yaml | 8 group contains 32 pins. GPIO_00~GPIO_1F belong to the Port0 group,
14 ex.Port0 group GPIO_00~GPIO_0F shares IRQ18, and Port0 group
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | davicom,dm8806-phy.yaml | 27 Port0: (5-bit PHY Address) + (5-bit Register address) = Absolute address
30 which is responsible for Ethernet Port0 in Davicom DM8806
45 Port0: (5bit PHY Address) + (5bit Register address) = Absolute address
48 which is responsible for Ethernet Port0 in Davicom DM8806
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| /Zephyr-latest/samples/subsys/usb_c/sink/boards/ |
| D | numaker_m2l31ki.overlay | 7 usbc-port0 = &port0;
14 port0: usbc-port@0 {
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| D | stm32g081b_eval.overlay | 12 usbc-port0 = &port1;
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| D | b_g474e_dpow1.overlay | 12 usbc-port0 = &port1;
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| /Zephyr-latest/samples/drivers/ps2/boards/ |
| D | mec172xmodular_assy6930.overlay | 9 ps2-port0 = &ps2_0;
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| D | mec172xevb_assy6906.overlay | 14 ps2-port0 = &ps2_0;
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| D | npcx7m6fb_evb.overlay | 9 ps2-port0 = &ps2_channel0;
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| D | npcx9m6f_evb.overlay | 9 ps2-port0 = &ps2_channel0;
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| D | mec1501modular_assy6885.overlay | 19 ps2-port0 = &ps2_0;
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| D | mec15xxevb_assy6853.overlay | 19 ps2-port0 = &ps2_0;
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| /Zephyr-latest/tests/drivers/gpio/gpio_api_1pin/boards/ |
| D | aw9523b_on_arduino_header.overlay | 12 port0-push-pull;
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| /Zephyr-latest/samples/subsys/usb_c/source/boards/ |
| D | stm32g081b_eval.overlay | 12 usbc-port0 = &port1;
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| /Zephyr-latest/boards/m5stack/m5stack_cores3/ |
| D | m5stack_cores3_procpu_common.dtsi | 96 port0-push-pull;
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_aw9523b.c | 172 LOG_ERR("%s: Failed to read port0 status (%d)", dev->name, err); in gpio_aw9523b_port_read_write_toggle()
471 /* Configure port0 to push-pull mode */ in gpio_aw9523b_init()
474 LOG_ERR("%s: Failed to configure port0 to push-pull (%d)", dev->name, err); in gpio_aw9523b_init()
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| D | gpio_pca95xx.c | 158 * @param reg Register to read (the PORT0 of the pair of registers).
225 * @param reg Register to write into (the PORT0 of the pair of registers).
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| /Zephyr-latest/boards/weact/stm32g431_core/ |
| D | weact_stm32g431_core.dts | 30 usbc-port0 = &usbc1;
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| /Zephyr-latest/samples/subsys/usb_c/sink/src/ |
| D | main.c | 302 LOG_ERR("PORT0 device not ready"); in main()
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| /Zephyr-latest/samples/subsys/usb_c/source/src/ |
| D | main.c | 322 LOG_ERR("PORT0 device not ready"); in main()
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| /Zephyr-latest/boards/adi/eval_adin1110ebz/doc/ |
| D | index.rst | 136 $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0
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| /Zephyr-latest/boards/adi/eval_adin2111ebz/doc/ |
| D | index.rst | 137 $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 30 * 0x3700 (port0 register base), instead of 0x3800 (port1 register base).
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| /Zephyr-latest/soc/ite/ec/common/ |
| D | chip_chipregs.h | 748 /* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
826 /* 0xE4: Port0 MISC Control Register */
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