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/hal_gigadevice-latest/scripts/tests/gd32pinctrl/data/
Dgd32f999xx.yml44 PA2:
63 pins: [PA2, null, PA3, PA4]
67 pins: [PA4, null, PA5, PA2]
69 pins: [PA5, null, PA2, PA3]
Dgd32f888xx.yml37 PA2:
/hal_gigadevice-latest/pinconfigs/
Dgd32e507xx.yml708 PA2:
1077 pins: [PA2, PB6]
1119 pins: [PA2, PA2, PB10, PB10]
1141 pins: [PA2, PE5]
1165 pins: [PA2, PD5]
Dgd32e103xx.yml457 PA2:
712 pins: [PA2, PB6]
746 pins: [PA2, PA2, PB10, PB10]
780 pins: [PA2, PD5]
Dgd32vf103xx.yml390 PA2:
683 pins: [PA2, PA2, PB10, PB10]
717 pins: [PA2, PD5]
Dgd32f403xx.yml491 PA2:
894 pins: [PA2, PE5]
918 pins: [PA2, PD5]
DREADME.md177 | USART0_TX | PA2, PA14 |
Dgd32f350xx.yml110 PA2:
Dgd32a503xx.yml50 PA2:
Dgd32l233xx.yml221 PA2:
Dgd32f405xx.yml54 PA2:
Dgd32f407xx.yml60 PA2:
Dgd32f450xx.yml59 PA2:
Dgd32f470xx.yml59 PA2:
/hal_gigadevice-latest/gd32e50x/standard_peripheral/include/
Dgd32e50x_cmp.h108 CMP_PA2, /*!< PA2 input */
139 … CS_CMPMSEL(6) /*!< CMP inverting input PA2 */
Dgd32e50x_pmu.h129 #define PMU_WAKEUP_PIN3 PMU_CS0_WUPEN3 /*!< WKUP Pin 3 (PA2) enable */
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_cmp.h87 …CMP_PA_0_2 /*!< PA0 or PA2 input …
162 …P1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_pmu.c284 \arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PA2)
301 \arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PA2)
Dgd32l23x_cmp.c70 \arg CMP_PA0_PA2: PA0 input when selecting CMP0, PA2 input when selecting CMP1
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_pmu.c406 \arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
426 \arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
Dgd32e50x_cmp.c64 \arg CMP_PA2: PA2 input(only CMP1)
Dgd32e50x_gpio.c418 \arg AFIO_PA2_CMP1_CFG: configure PA2 alternate function to CMP1
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_cmp.h91 … /*!< PA0 input when selecting CMP0, PA2 input when selectin…
231 …1MSEL_PA2 CS_CMP1MSEL(4) /*!< CMP1 inverting input PA2 */
Dgd32l23x_pmu.h161 #define PMU_WAKEUP_PIN2 PMU_CS_WUPEN2 /*!< WKUP Pin 2 (PA2) */
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_cmp.c67 \arg CMP_PA_0_2: PA0 or PA2 input

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