| /Zephyr-latest/boards/beagle/beaglebone_ai64/ |
| D | beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi | 13 /* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */
18 /* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
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| /Zephyr-latest/subsys/logging/frontends/ |
| D | log_frontend_stmesp.c | 218 const uint8_t *p8 = data; in write_data() local
236 STM_D8(stm_esp, *p8++, false, false); in write_data()
237 STM_D16(stm_esp, *(uint16_t *)p8, false, false); in write_data()
238 p8 += sizeof(uint16_t); in write_data()
242 STM_D16(stm_esp, *(uint16_t *)p8, false, false); in write_data()
243 p8 += sizeof(uint16_t); in write_data()
249 STM_D8(stm_esp, *p8++, false, false); in write_data()
250 STM_D8(stm_esp, *p8++, false, false); in write_data()
255 STM_D8(stm_esp, *p8++, false, false); in write_data()
259 p32 = (const uint32_t *)p8; in write_data()
[all …]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | nordic-thingy53-edge-connector.yaml | 13 P8 P0.05/AIN1
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| /Zephyr-latest/boards/adafruit/nrf52_adafruit_feather/ |
| D | board.h | 26 #define EXT_RXD_GPIO_PIN 8 /* P8 */
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| /Zephyr-latest/boards/bbc/microbit/ |
| D | board.h | 23 #define EXT_P8_GPIO_PIN 18 /* P8 */
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| D | bbc_microbit.dts | 91 <8 0 &gpio0 18 0>, /* P8 */
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ifx_cat1-pinctrl.h | 82 #define P8 CYHAL_PORT_8 macro
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| /Zephyr-latest/boards/beagle/beaglebone_ai64/doc/ |
| D | index.rst | 114 Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | ite,it8xxx2-pinctrl.yaml | 31 gpio-voltage = "1p8";
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| /Zephyr-latest/drivers/sensor/bosch/bmp388/ |
| D | bmp388.h | 165 int8_t p8; member
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| D | bmp388.c | 339 partial_data4 = (cal->p8 * partial_data3) / 32; in bmp388_compensate_press()
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| /Zephyr-latest/boards/nordic/thingy53/ |
| D | thingy53_nrf5340_cpunet.dts | 77 <8 0 &gpio0 5 0>, /* P8, P0.05/AIN1 */
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| D | thingy53_nrf5340_common.dtsi | 71 gpio-map = <8 0 &gpio0 5 0>, /* P8, P0.05/AIN1 */
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| /Zephyr-latest/boards/beagle/beaglev_fire/doc/ |
| D | index.rst | 9 RISC-V architecture and FPGA technology. It has the same P8 & P9 cape header pins as BeagleBone
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| /Zephyr-latest/boards/bbc/microbit_v2/ |
| D | bbc_microbit_v2.dts | 90 <8 0 &gpio0 10 0>, /* P8 */
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| /Zephyr-latest/boards/st/steval_fcu001v1/doc/ |
| D | index.rst | 106 The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter.
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| /Zephyr-latest/boards/adi/sdp_k1/doc/ |
| D | index.rst | 113 - UART_5 TX/RX : P8 (DAPLink two position through hole)
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| /Zephyr-latest/scripts/tests/twister/ |
| D | test_hardwaremap.py | 31 DUT(platform='p8', id=8, serial='s8', product='pr8', connected=False)
711 | p8 | 8 | s8 |
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| /Zephyr-latest/drivers/espi/ |
| D | espi_mchp_xec.c | 450 uint8_t *p8 = (uint8_t *)®->SRC; in espi_xec_send_vwire() local
452 *(p8 + (uintptr_t) src_id) = level; in espi_xec_send_vwire()
457 uint8_t *p8 = (uint8_t *)®->SRC; in espi_xec_send_vwire() local
459 *(p8 + (uintptr_t) src_id) = level; in espi_xec_send_vwire()
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_mchp_xec_v2.c | 737 uint8_t *p8 = &msg->buf[0]; in ctrl_rx() local
751 *p8++ = temp; in ctrl_rx()
766 *p8 = regs->I2CDATA; in ctrl_rx()
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| /Zephyr-latest/drivers/wifi/eswifi/ |
| D | eswifi_socket.c | 272 snprintk(eswifi->buf, sizeof(eswifi->buf), "P8=%d\r", backlog); in __eswifi_listen()
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| D | eswifi_offload.c | 52 snprintk(eswifi->buf, sizeof(eswifi->buf), "P8=%d\r", backlog); in eswifi_off_listen()
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| /Zephyr-latest/boards/madmachine/mm_feather/doc/ |
| D | index.rst | 103 | P8 | GPIO_AD_B1_13 | D8 | GPIO1_IO29 | | |
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| /Zephyr-latest/boards/madmachine/mm_swiftio/doc/ |
| D | index.rst | 83 | P8 | GPIO_B0_01 | D8 | GPIO2_IO01 | | |
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| /Zephyr-latest/boards/nordic/nrf52dk/doc/ |
| D | index.rst | 263 P2/P8 Analog in
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