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Searched +full:non +full:- +full:maskable (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/samples/drivers/watchdog/boards/
Dcc26x2r1_launchxl.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
Dcc1352r1_launchxl.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
Dcc1352r1_sensortag.overlay2 /* uncomment to use Non-Maskable interrupt instead of the normal one */
3 /* interrupt-nmi; */
/Zephyr-latest/dts/bindings/watchdog/
Dti,cc13xx-cc26xx-watchdog.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ti,cc13xx-cc26xx-watchdog"
17 interrupt-nmi:
20 Whether the watchdog triggers a Non-Maskable Interrupt or a standard one
/Zephyr-latest/dts/bindings/clock/
Dst,stm32-hse-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "st,stm32-hse-clock"
8 include: [fixed-clock.yaml]
11 hse-bypass:
15 Set to the property to by-pass the oscillator with an external clock.
17 css-enabled:
24 a clock failure event is sent to timers, and a non-maskable interrupt is generated to
28 The interaction of CSS and low-power modes is unclear from the documentation.
29 For at least some devices Zephyr will reconfigure the clocks on resuming from low-power
30 modes; this will include re-enabling CSS. However it is important that you verify
/Zephyr-latest/soc/intel/intel_adsp/ace/
D_soc_inthandlers.h2 * SPDX-License-Identifier: Apache-2.0
16 #include <xtensa/config/core-isa.h>
21 #error core-isa.h interrupt level does not match dispatcher!
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/boards/native/native_posix/
Dcpu_wait.c4 * SPDX-License-Identifier: Apache-2.0
28 * programming a dedicated timer which will raise a non-maskable interrupt,
54 * time would be spent on interrupt handling or possible switched-in tasks.
71 to_wait -= hwm_get_time() - time_start; in posix_cpu_hold()
/Zephyr-latest/boards/native/native_sim/
Dcpu_wait.c5 * SPDX-License-Identifier: Apache-2.0
31 * programming a dedicated timer which will raise a non-maskable interrupt,
57 * time would be spent on interrupt handling or possible switched-in tasks.
74 to_wait -= nsi_hws_get_time() - time_start; in posix_cpu_hold()
/Zephyr-latest/doc/hardware/peripherals/edac/
Dibecc.rst12 The In-Band Error Correction Code (IBECC) improves reliability by providing
15 not support the out-of-band ECC.
58 * Correctable Error (CE) - error is detected and corrected by IBECC module.
60 * Uncorrectable Error (UE) - error is detected by IBECC module and not
63 The IBECC driver provides error type for the higher-level application to
65 syndrome is not used in the IBECC driver but provided to higher-level
71 Exceptional care needs to be taken with Non Maskable Interrupt (NMI). NMI will
75 higher-level synchronization primitives. So, you cannot share anything that is
/Zephyr-latest/soc/arm/beetle/
DCMSDK_BEETLE.h2 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
4 * SPDX-License-Identifier: Apache-2.0
20 /* ------------------------- Interrupt Number Definition ------------------------ */
24 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
25 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
26 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
27 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
28 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
29 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
30 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
[all …]
/Zephyr-latest/soc/brcm/bcmvk/valkyrie/
Dsoc.h1 /* SPDX-License-Identifier: Apache-2.0 */
17 /* CORTEX-M7 Processor Exceptions Numbers */
18 NonMaskableInt_IRQn = -14, /*< 2 Non Maskable Interrupt */
19 HardFault_IRQn = -13, /*< 3 HardFault Interrupt */
20 MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt */
21 BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt */
22 UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt */
23 SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt */
24 DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt */
25 PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt */
[all …]
/Zephyr-latest/soc/brcm/bcmvk/viper/m7/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
18 /* CORTEX-M7 Processor Exceptions Numbers */
19 NonMaskableInt_IRQn = -14, /*< 2 Non Maskable Interrupt */
20 HardFault_IRQn = -13, /*< 3 HardFault Interrupt */
21 MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt */
22 BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt */
23 UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt */
24 SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt */
25 DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt */
26 PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt */
[all …]
/Zephyr-latest/soc/arm/musca/b1/
Dsystem_cmsdk_musca_b1.h2 * Copyright (c) 2017-2019 Arm Limited
4 * SPDX-License-Identifier: Apache-2.0
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
30 …SVCall_IRQn = -5, /* -5 SV Call Interrupt …
31 …DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt …
[all …]
/Zephyr-latest/soc/arm/musca/s1/
Dsystem_cmsdk_musca_s1.h2 * Copyright (c) 2017-2020 Arm Limited
4 * SPDX-License-Identifier: Apache-2.0
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
30 …SVCall_IRQn = -5, /* -5 SV Call Interrupt …
31 …DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt …
[all …]
/Zephyr-latest/arch/sparc/core/
Dfatal.c2 * Copyright (c) 2019-2020 Cobham Gaisler AB
4 * SPDX-License-Identifier: Apache-2.0
14 * ---------------------------------------------------------------------
36 * ---------------------------------------------------------------------
65 * highest level where only non-maskable interrupts are taken.
99 * manual, Table 7-1.
127 const int tt = (esf->tbr & TBR_TT) >> TBR_TT_BIT; in print_trap_type()
147 const struct savearea *flushed = (struct savearea *) esf->out[6]; in print_integer_registers()
154 flushed ? flushed->in[i] : 0, in print_integer_registers()
155 flushed ? flushed->local[i] : 0, in print_integer_registers()
[all …]
/Zephyr-latest/arch/x86/core/
Dfatal.c3 * SPDX-License-Identifier: Apache-2.0
22 * -device isa-debug-exit,iobase=0xf4,iosize=0x04 in arch_system_halt()
27 * It has been observed that if the emulator exits for a triple-fault in arch_system_halt()
41 return esf->rsp; in esf_get_sp()
43 return esf->esp; in esf_get_sp()
58 cpu_id = arch_curr_cpu()->id; in z_x86_check_stack_bounds()
67 (arch_current_thread()->base.user_options & K_USER) != 0) { in z_x86_check_stack_bounds()
75 start = arch_current_thread()->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; in z_x86_check_stack_bounds()
76 end = arch_current_thread()->stack_info.start; in z_x86_check_stack_bounds()
80 start = arch_current_thread()->stack_info.start; in z_x86_check_stack_bounds()
[all …]