| /Zephyr-latest/dts/bindings/interrupt-controller/ |
| D | cypress,psoc6-intmux.yaml | 8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
18 directly connected to NVIC and doesn't require any special configuration.
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
32 sources and the proper NVIC interrupt order. With that, the system configures
39 Cortex-M0+ NVIC:
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| D | arm,v7m-nvic.yaml | 1 description: ARMv7-M NVIC (Nested Vectored Interrupt Controller)
3 compatible: "arm,v7m-nvic"
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| D | arm,v8m-nvic.yaml | 1 description: ARMv8-M NVIC (Nested Vectored Interrupt Controller)
3 compatible: "arm,v8m-nvic"
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| D | arm,v6m-nvic.yaml | 1 description: ARMv6-M NVIC (Nested Vectored Interrupt Controller) controller
3 compatible: "arm,v6m-nvic"
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| D | arm,v8.1m-nvic.yaml | 1 description: ARMv8.1-M NVIC (Nested Vectored Interrupt Controller)
3 compatible: "arm,v8.1m-nvic"
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| /Zephyr-latest/soc/nordic/nrf54h/ |
| D | pm_s2ram.c | 28 /* NVIC components stored into RAM. */
98 memcpy(backup->ISER, (uint32_t *)NVIC->ISER, sizeof(NVIC->ISER)); in nvic_suspend()
99 memcpy(backup->ISPR, (uint32_t *)NVIC->ISPR, sizeof(NVIC->ISPR)); in nvic_suspend()
100 memcpy(backup->IPR, (uint32_t *)NVIC->IPR, sizeof(NVIC->IPR)); in nvic_suspend()
105 memcpy((uint32_t *)NVIC->ISER, backup->ISER, sizeof(NVIC->ISER)); in nvic_resume()
106 memcpy((uint32_t *)NVIC->ISPR, backup->ISPR, sizeof(NVIC->ISPR)); in nvic_resume()
107 memcpy((uint32_t *)NVIC->IPR, backup->IPR, sizeof(NVIC->IPR)); in nvic_resume()
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| /Zephyr-latest/dts/arm/ |
| D | armv6-m.dtsi | 10 interrupt-parent = <&nvic>;
13 nvic: interrupt-controller@e000e100 { label
15 compatible = "arm,v6m-nvic";
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| D | armv7-m.dtsi | 10 interrupt-parent = <&nvic>;
13 nvic: interrupt-controller@e000e100 { label
15 compatible = "arm,v7m-nvic";
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| D | armv8-m.dtsi | 10 interrupt-parent = <&nvic>;
13 nvic: interrupt-controller@e000e100 { label
15 compatible = "arm,v8m-nvic";
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| D | armv8.1-m.dtsi | 14 interrupt-parent = <&nvic>;
17 nvic: interrupt-controller@e000e100 { label
19 compatible = "arm,v8.1m-nvic";
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| /Zephyr-latest/tests/arch/arm/arm_irq_advanced_features/src/ |
| D | arm_zero_latency_irqs.c | 30 /* Determine an NVIC IRQ line that is not currently in use. */ in ZTEST()
48 /* Set the NVIC line to pending. */ in ZTEST()
53 * If the NVIC line is pending, it is in ZTEST()
61 * If the NVIC line can be successfully in ZTEST()
64 * triggering. Return the NVIC line in ZTEST()
95 * Instruction barriers to make sure the NVIC IRQ is in ZTEST()
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| D | arm_irq_target_state.c | 20 /* Determine an NVIC IRQ line that is implemented in ZTEST()
35 /* Set the NVIC line to pending. */ in ZTEST()
39 /* If the NVIC line is pending, it is in ZTEST()
46 * If the NVIC line can be successfully in ZTEST()
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| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | irq_manage.c | 49 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in arch_irq_is_enabled()
157 * to NVIC.ITNS register is write-ignored(WI), as the ITNS register is not
196 * to NVIC.ITNS register is read-as-zero(RAZ), as the ITNS register is not
212 * The function is used to set all HW NVIC interrupt lines to target the
216 * - All NVIC interrupts are disabled before being routed to Non-Secure.
225 /* Disable (Clear) all NVIC interrupt lines. */ in irq_target_state_set_all_non_secure()
226 for (i = 0; i < sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]); i++) { in irq_target_state_set_all_non_secure()
227 NVIC->ICER[i] = 0xFFFFFFFF; in irq_target_state_set_all_non_secure()
233 /* Set all NVIC interrupt lines to target Non-Secure */ in irq_target_state_set_all_non_secure()
234 for (i = 0; i < sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0]); i++) { in irq_target_state_set_all_non_secure()
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| D | scb.c | 107 /* Disable NVIC interrupts */ in z_arm_init_arch_hw_at_boot()
108 for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICER); i++) { in z_arm_init_arch_hw_at_boot()
109 NVIC->ICER[i] = 0xFFFFFFFF; in z_arm_init_arch_hw_at_boot()
111 /* Clear pending NVIC interrupts */ in z_arm_init_arch_hw_at_boot()
112 for (uint8_t i = 0; i < ARRAY_SIZE(NVIC->ICPR); i++) { in z_arm_init_arch_hw_at_boot()
113 NVIC->ICPR[i] = 0xFFFFFFFF; in z_arm_init_arch_hw_at_boot()
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| /Zephyr-latest/tests/drivers/build_all/i2c/boards/ |
| D | qemu_cortex_m3.overlay | 15 interrupt-parent = <&nvic>;
24 interrupt-parent = <&nvic>;
34 interrupt-parent = <&nvic>;
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| /Zephyr-latest/dts/arm/broadcom/ |
| D | viper-m7.dtsi | 30 &nvic {
43 interrupt-parent = <&nvic>;
50 interrupt-parent = <&nvic>;
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| /Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/ |
| D | mchp-xec-ecia.h | 13 * na = bits[23:16], aggregated GIRQ NVIC number
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
17 * are not connected to the NVIC. Use 255 for na and nd.
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | soc.c | 16 * Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
41 /* Clear all external NVIC enables and pending status */ in soc_ecia_init()
43 NVIC->ICER[n] = 0xFFFFFFFFul; in soc_ecia_init()
44 NVIC->ICPR[n] = 0xFFFFFFFFul; in soc_ecia_init()
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| /Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/ |
| D | arm_custom_interrupt.c | 57 return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq)); in z_soc_irq_is_enabled()
127 /* Determine an NVIC IRQ line that is not currently in use. */ in ZTEST()
140 /* Set the NVIC line to pending. */ in ZTEST()
144 /* If the NVIC line is pending, it is in ZTEST()
152 * If the NVIC line can be successfully in ZTEST()
189 * Instruction barriers to make sure the NVIC IRQ is in ZTEST()
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| /Zephyr-latest/tests/arch/arm/arm_irq_zero_latency_levels/src/ |
| D | main.c | 119 /* Set the NVIC line to pending. */ in find_unused_irq()
124 * If the NVIC line is pending, it is in find_unused_irq()
132 * If the NVIC line can be successfully in find_unused_irq()
135 * triggering. Return the NVIC line in find_unused_irq()
163 /* Determine two NVIC IRQ lines that are not currently in use. */ in ZTEST()
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| /Zephyr-latest/dts/arm/ti/ |
| D | am64x_m4.dtsi | 52 interrupt-parent = <&nvic>;
63 interrupt-parent = <&nvic>;
80 &nvic {
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| /Zephyr-latest/subsys/testsuite/include/zephyr/ |
| D | interrupt_util.h | 30 /* Set the NVIC line to pending. */ in get_available_nvic_line()
35 * If the NVIC line is pending, it is in get_available_nvic_line()
43 * If the NVIC line can be successfully in get_available_nvic_line()
46 * triggering. Return the NVIC line in get_available_nvic_line()
69 NVIC->STIR = irq; in trigger_irq()
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| /Zephyr-latest/tests/arch/arm/arm_no_multithreading/src/ |
| D | main.c | 96 /* Determine an NVIC IRQ line that is not currently in use. */ in test_main()
111 /* Set the NVIC line to pending. */ in test_main()
115 /* If the NVIC line is pending, it is in test_main()
123 * If the NVIC line can be successfully in test_main()
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| /Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/ |
| D | cypress_psoc6_dt.h | 24 * multiplexers in front of any NVIC interrupt line.
47 * Cortex-M4 simple pass the parameter and constructs an usual NVIC
52 * Cortex-M0+ NVIC. The multiplexer is configured by CY_PSOC6_DT_NVIC_MUX_MAP
76 * since it uses interrupt-parent, and the value at Cortex-M0 NVIC multiplexers
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| /Zephyr-latest/arch/arm/ |
| D | Kconfig | 21 non-GIC or NVIC) interrupt controller.
27 the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
33 N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
35 assumes responsibility for handling the NVIC.
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