Lines Matching full:nvic
8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
18 directly connected to NVIC and doesn't require any special configuration.
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
32 sources and the proper NVIC interrupt order. With that, the system configures
39 Cortex-M0+ NVIC:
59 These results in Cortex-M0+ NVIC line 20 handling PSOC 6 interrupt source 2.
60 The interrupt can be enabled/disabled at NVIC at line 20 as usual.
66 3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels