Searched full:neorv32 (Results 1 – 25 of 32) sorted by relevance
12
1 .. zephyr:board:: neorv326 The NEORV32 is an open-source RISC-V compatible processor system intended as a10 For more information about the NEORV32, see the following websites:12 - `The NEORV32 RISC-V Processor GitHub`_13 - `The NEORV32 RISC-V Processor Datasheet`_14 - `The NEORV32 RISC-V Processor User Guide`_21 The ``neorv32`` board configuration can be used a generic definition for NEORV3222 based boards. Customisation to fit custom NEORV32 implementations can be done25 Zephyr currently supports the following hardware features of the NEORV3243 The default board configuration for the NEORV32 Processor (SoC) can be found in[all …]
5 # Generate NEORV32 image formats for initialising IMEM.17 …message(STATUS "neorv32 binary will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}…27 …message(STATUS "neorv32 VHDL will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.v…29 …message(STATUS "The neorv32 image_gen utility was not found, neorv32 image files cannot be generat…
2 name: neorv323 full_name: NEORV3211 - name: neorv32
1 identifier: neorv322 name: NEORV32 Processor (SoC)
9 #include <neorv32.dtsi>14 model = "NEORV32";15 compatible = "neorv32";
7 NEORV32 Processor (SoC).9 The NEORV32 CPU implementation must have the following RISC-V ISA14 The following NEORV32 CPU ISA extensions are not currently supported22 default "neorv32" if SOC_NEORV32
19 # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO26 The targeted NEORV32 version as BCD-coded number. The format is27 identical to that of the NEORV32 Machine implementation ID (mimpid)34 Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
2 - name: neorv32
17 * The MIP CSR on the NEORV32 is read-only and can thus not be used for
1 description: NEORV32 True Random Number Generator (TRNG)3 compatible: "neorv32-trng"15 phandle to syscon (NEORV32 SYSINFO) node.
1 # NEORV32 GPIO configuration options7 bool "NEORV32 GPIO driver"12 Enable NEORV32 GPIO driver.
1 # NEORV32 UART configuration7 bool "NEORV32 UART"14 This option enables the UART driver for the NEORV32.
1 description: NEORV32 UART3 compatible: "neorv32-uart"24 phandle to syscon (NEORV32 SYSINFO) node.
1 # NEORV32 TRNG configuration7 bool "NEORV32 TRNG"14 the NEORV32.
35 source "drivers/entropy/Kconfig.neorv32"
103 LOG_ERR("neorv32 trng not supported"); in neorv32_trng_init()
5 NEORV32 Machine Timer7 The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp10 compatible: "neorv32-machine-timer"
1 description: NEORV32 GPIO3 compatible: "neorv32-gpio"18 phandle to syscon (NEORV32 SYSINFO) node.
22 compatible = "neorv32-cpu", "riscv";68 compatible = "neorv32-machine-timer";74 compatible = "neorv32-uart";83 compatible = "neorv32-trng";103 compatible = "neorv32-gpio";114 compatible = "neorv32-gpio";126 compatible = "neorv32-uart";
4 description: NEORV32 RISC-V CPU6 compatible: "neorv32-cpu"
12 - neorv32
17 source [find neorv32.cfg]
7 set _CHIPNAME neorv32
16 - neorv32
9 and support for some FPGA implementations such as neorv32 and
