| /Zephyr-latest/dts/bindings/mdio/ |
| D | zephyr,mdio-gpio.yaml | 11 mdc-gpios:
14 description: GPIO pin for the MDC
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| D | mdio-controller.yaml | 30 Some MDIO controllers have the ability to configure the MDC frequency.
31 If present, this property may be used to specify the MDC frequency based
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| D | nxp,s32-gmac-mdio.yaml | 8 interface (MDC/MDIO), implemented as per IEEE 802.3 specification. SMA
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| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm4.dtsi | 14 mdc: mdc@4000c000 { label
20 mdc_header: mdc@4000c00a {
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| D | npcm.dtsi | 26 mdc: mdc@4000c000 { label
32 mdc_header: mdc@4000c00a {
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| /Zephyr-latest/include/zephyr/dt-bindings/ethernet/ |
| D | xlnx_gem.h | 13 * MDC divider values
18 * as it claims that the MDC clock division is applied to the cpu_1x clock
21 * the PHY", p. 1074, that the MDC clock division is applied to the IOU_SWITCH_CLK.
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| /Zephyr-latest/tests/drivers/build_all/mdio/ |
| D | app.overlay | 29 mdc-gpios = <&test_gpio 0 0>;
39 mdc-gpios = <&test_gpio 0 0>;
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | silabs,gecko-ethernet.yaml | 36 description: location of MDC and MDIO pins, configuration defined as <location>
42 description: PHY MDC individual pin configuration defined as <location port pin>
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| D | xlnx,gem.yaml | 31 mdc-divider:
35 The MDC clock divider for the respective GEM. This is the divider
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| /Zephyr-latest/boards/qemu/cortex_a9/ |
| D | qemu_cortex_a9.dts | 61 mdc-divider = <XLNX_GEM_MDC_DIVIDER_224>;
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| /Zephyr-latest/drivers/mdio/ |
| D | mdio_gpio.c | 136 LOG_ERR("GPIO port for MDC pin is not ready"); in mdio_gpio_initialize()
147 LOG_ERR("Couldn't configure MDC pin; (%d)", rc); in mdio_gpio_initialize()
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| D | mdio_xmc4xxx.c | 130 LOG_DBG("Using MDC clock divider %d", divider); in mdio_xmc4xxx_set_clock_divider()
131 LOG_DBG("MDC clock %dHz", mdc_clk); in mdio_xmc4xxx_set_clock_divider()
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| /Zephyr-latest/tests/drivers/build_all/ethernet/ |
| D | app.overlay | 24 mdc-gpios = <&test_gpio 0 0>;
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_smsc91x.c | 29 #define MDC MGMT_MCLK macro
176 smsc_mii_bitbang_write(sc, v | MDC); in smsc_miibus_sync()
197 smsc_mii_bitbang_write(sc, v | MDC); in smsc_miibus_sendbits()
220 smsc_mii_bitbang_write(sc, MDIRHOST | MDC); in smsc_miibus_readreg()
227 smsc_mii_bitbang_write(sc, MDIRHOST | MDC); in smsc_miibus_readreg()
238 smsc_mii_bitbang_write(sc, MDIRHOST | MDC); in smsc_miibus_readreg()
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| D | eth_xlnx_gem_priv.h | 249 * [20 .. 18] MDC clock division setting
574 * @brief MDC clock divider configuration enumeration type.
577 * used to generate the MDIO interface clock (MDC) from either the
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| D | eth_xlnx_gem.c | 121 /* MDC clock divider validity check, SoC dependent */ in DT_INST_FOREACH_STATUS_OKAY()
124 "%s invalid MDC clock divider value %u, must be in " in DT_INST_FOREACH_STATUS_OKAY()
129 "%s invalid MDC clock divider value %u, must be in " in DT_INST_FOREACH_STATUS_OKAY()
945 /* [20..18] MDC clock divider */ in eth_xlnx_gem_set_initial_nwcfg()
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| D | eth_sam_gmac.c | 833 * Set MCK to MDC clock divisor.
835 * According to 802.3 MDC should be less then 2.5 MHz.
854 LOG_ERR("No valid MDC clock"); in get_mck_clock_divisor()
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| D | eth_stm32_hal.c | 1017 /* Adjust MDC clock range depending on HCLK frequency: */ in eth_initialize()
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| /Zephyr-latest/drivers/serial/ |
| D | uart_ns16550.c | 255 #define MDC(dev) (get_port(dev) + (REG_MDC * reg_interval(dev))) macro
574 uint8_t mdc = 0U, c; local
686 mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
690 mdc |= MCR_AFCE;
694 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
1342 uint32_t mdc, chg, pclk = 0U; local
1361 mdc = ns16550_inbyte(dev_cfg, MDC(dev));
1370 mdc |= chg;
1372 mdc &= ~(chg);
1374 ns16550_outbyte(dev_cfg, MDC(dev), mdc);
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| D | uart_mchp_xec.c | 970 uint32_t mdc, chg; in uart_xec_line_ctrl_set() local
981 mdc = regs->MCR; in uart_xec_line_ctrl_set()
990 mdc |= chg; in uart_xec_line_ctrl_set()
992 mdc &= ~(chg); in uart_xec_line_ctrl_set()
994 regs->MCR = mdc; in uart_xec_line_ctrl_set()
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx.dtsi | 90 mdc: mdc@4000c000 { label
96 mdc_header: mdc@4000c00a {
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| /Zephyr-latest/boards/espressif/esp32_ethernet_kit/doc/ |
| D | index.rst | 292 8 GPIO23 MDC
388 IO23,MDC,,,,
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| /Zephyr-latest/boards/atmel/sam0/same54_xpro/doc/ |
| D | index.rst | 122 - GMAC MDIO MDC : PC11
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