| /Zephyr-latest/boards/brcm/bcm958402m2/doc/ |
| D | m7.rst | 3 Broadcom BCM958402M2 (Cortex-M7)
8 The Broadcom ``bcm958402m2/bcm58402/m7`` board utilizes the Viper BCM58402_M7 SoC to
13 The ``bcm958402m2/bcm58402/m7`` is a PCIe card with the following physical features:
21 The Broadcom ``bcm958402m2/bcm58402/m7`` board configuration supports the following
48 The ``bcm958402m2/bcm58402/m7`` board includes pads for soldering a JTAG connector.
49 Zephyr applications running on the M7 core can also be tested
|
| /Zephyr-latest/dts/bindings/cpu/ |
| D | arm,cortex-m7.yaml | 4 description: ARM Cortex-M7 CPU
6 compatible: "arm,cortex-m7"
|
| /Zephyr-latest/boards/arduino/portenta_h7/ |
| D | arduino_portenta_h7_stm32h747xx_m7.yaml | 1 identifier: arduino_portenta_h7/stm32h747xx/m7
2 name: Arduino Portenta H7 (M7)
|
| /Zephyr-latest/soc/brcm/bcmvk/valkyrie/ |
| D | soc.h | 17 /* CORTEX-M7 Processor Exceptions Numbers */
20 MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt */
21 BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt */
22 UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt */
23 SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt */
24 DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt */
25 PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt */
26 SysTick_IRQn = -1, /*< 15 Cortex-M7 System Tick Interrupt */
278 * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals
|
| /Zephyr-latest/boards/arduino/nicla_vision/ |
| D | arduino_nicla_vision_stm32h747xx_m7.yaml | 1 identifier: arduino_nicla_vision/stm32h747xx/m7
2 name: Arduino Nicla Vision (M7)
|
| /Zephyr-latest/boards/arduino/giga_r1/ |
| D | arduino_giga_r1_stm32h747xx_m7.yaml | 1 identifier: arduino_giga_r1/stm32h747xx/m7
2 name: Arduino GIGA R1 WiFi (M7)
|
| /Zephyr-latest/boards/st/stm32h747i_disco/ |
| D | stm32h747i_disco_stm32h747xx_m7.yaml | 1 identifier: stm32h747i_disco/stm32h747xx/m7
2 name: ST STM32H747I Discovery (M7)
|
| /Zephyr-latest/boards/st/nucleo_h755zi_q/ |
| D | nucleo_h755zi_q_stm32h755xx_m7.yaml | 1 identifier: nucleo_h755zi_q/stm32h755xx/m7
2 name: ST Nucleo H755ZI-Q (M7)
|
| /Zephyr-latest/boards/arduino/opta/ |
| D | arduino_opta_stm32h747xx_m7.yaml | 1 identifier: arduino_opta/stm32h747xx/m7
2 name: ARDUINO OPTA (M7)
|
| D | arduino_opta_stm32h747xx_m7.dts | 15 model = "Arduino OPTA M7 core Programmable Logic Controller";
16 compatible = "arduino,opta-m7";
89 /* Assign USB to M7 by default */
98 /* Assign ethernet to M7 by default */
|
| /Zephyr-latest/boards/st/nucleo_h745zi_q/ |
| D | nucleo_h745zi_q_stm32h745xx_m7.yaml | 1 identifier: nucleo_h745zi_q/stm32h745xx/m7
2 name: ST Nucleo H745ZI-Q (M7)
|
| /Zephyr-latest/boards/st/stm32h745i_disco/ |
| D | stm32h745i_disco_stm32h745xx_m7.yaml | 1 identifier: stm32h745i_disco/stm32h745xx/m7
2 name: STM32H745XI Discovery (M7)
|
| /Zephyr-latest/soc/brcm/bcmvk/viper/m7/ |
| D | soc.h | 18 /* CORTEX-M7 Processor Exceptions Numbers */
21 MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt */
22 BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt */
23 UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt */
24 SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt */
25 DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt */
26 PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt */
27 SysTick_IRQn = -1, /*< 15 Cortex-M7 System Tick Interrupt */
279 * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals
|
| /Zephyr-latest/boards/nxp/imx95_evk/doc/ |
| D | index.rst | 19 functional safety with built-in Arm Cortex-M33 and -M7 cores
76 The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardware features:
118 Cortex-M7 Core runs up to 800MHz in which SYSTICK runs on same frequency.
124 CPU's UART1 for Cortex-A55, UART3 for Cortex-M7.
129 Two channels are enabled on TPM2 for PWM for M7. Signals can be observerd with
221 Programming and Debugging (M7)
232 To program M7, an i.MX container image ``flash.bin`` must be made, which contains
233 multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cortex-M7
243 Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and
244 ``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory
[all …]
|
| /Zephyr-latest/tests/kernel/cache/ |
| D | testcase.yaml | 8 - bcm958402m2/bcm58402/m7
23 - bcm958402m2/bcm58402/m7
|
| /Zephyr-latest/soc/brcm/bcmvk/viper/ |
| D | CMakeLists.txt | 15 zephyr_include_directories(m7)
16 zephyr_sources(m7/soc.c)
|
| /Zephyr-latest/boards/phytec/phyboard_pollux/doc/ |
| D | index.rst | 11 Coretex-M7 core for real time applications like Zephyr. The phyBOARD-Pollux
79 It's recommended to disable peripherals used by the M7-Core on the host running
81 Zephyr on the M7-Core.
98 | Debug USB (M7) | UART4 | UART Debug Console via USB |
116 The i.MX8MP does not have a separate flash for the M7-Core. Because of this
117 the A53-Core has to load the program for the M7-Core to the right memory
120 The M7 can use up to 3 different RAMs (currently, only two configurations are
121 supported: ITCM and DDR). These are the memory mapping for A53 and M7:
124 | Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size |
175 A serial console for both the application CPU and the Cortex M7 coprocessor are
[all …]
|
| /Zephyr-latest/boards/nxp/imx8mp_evk/doc/ |
| D | index.rst | 7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
91 The M7 Core is configured to run at a 800 MHz clock speed.
159 Programming and Debugging (M7)
162 The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs
163 to be started by the A53 core. The A53 core is responsible to load the M7 binary
164 application into the RAM, put the M7 in reset, set the M7 Program Counter and
165 Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at
168 The M7 can use up to 3 different RAMs (currently, only two configurations are
169 supported: ITCM and DDR). These are the memory mapping for A53 and M7:
172 | Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size …
[all …]
|
| /Zephyr-latest/boards/arduino/opta/doc/ |
| D | index.rst | 19 the M4 making the M7 run the PLC tasks while the M4 core under Zephyr acts as
48 The ``arduino_opta/stm32h747xx/m7`` board target
101 Both the M7 and M4 cores have access to the 9 GPIO controllers. These
136 M7 clock is driven at 400MHz.
144 - **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
170 - CPU1 (Cortex-M7) boot address is set to 0x08040000
174 "Flash split: 1.5MB M7 + 0.5MB M4" option in the Arduino IDE. The flash is
178 - 0x08040000-0x080FFFFF (768k) M7 application
182 Flashing an application to ARDUINO OPTA M7
188 Here is an example for the :zephyr:code-sample:`blinky` application on M7 core.
[all …]
|
| /Zephyr-latest/boards/toradex/verdin_imx8mp/doc/ |
| D | index.rst | 42 The Arm® Cortex®-M7 microcontroller is indicated for Real-time control, combining high-performance
47 master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32
62 - RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
127 It is recommended to disable peripherals used by the M7 core on the Linux host.
164 The M7 Core is configured to run at a 800 MHz clock speed.
175 The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the
176 A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in
177 reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can
180 The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and
181 DDR). These are the memory mapping for A53 and M7:
[all …]
|
| /Zephyr-latest/tests/drivers/spi/spi_loopback/ |
| D | testcase.yaml | 61 - nucleo_h745zi_q/stm32h745xx/m7
79 - nucleo_h745zi_q/stm32h745xx/m7
93 - nucleo_h745zi_q/stm32h745xx/m7
104 - nucleo_h745zi_q/stm32h745xx/m7
116 - nucleo_h745zi_q/stm32h745xx/m7
131 - nucleo_h745zi_q/stm32h745xx/m7
|
| /Zephyr-latest/soc/nxp/imx/ |
| D | soc.yml | 25 - name: m7
45 - name: m7
|
| /Zephyr-latest/samples/boards/st/h7_dual_core/ |
| D | README.rst | 14 Build for stm32h747i_disco/stm32h747xx/m7:
18 :board: stm32h747i_disco/stm32h747xx/m7
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 20 /* Move M7 core to specific RDC domain 1 */ in SOC_RdcInit()
32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
87 * driver on M7 core side . Please note that the ROM has already configured the SYSTEM PLL1 in SOC_ClockInit()
90 * on M7 side, otherwise it would have a risk to make the SOC hang. in SOC_ClockInit()
96 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */ in SOC_ClockInit()
101 /* switch cortex-m7 to SYSTEM PLL1 */ in SOC_ClockInit()
162 /* The purpose to enable the following modules clock is to make sure the M7 core could work in SOC_ClockInit()
|
| /Zephyr-latest/dts/bindings/display/ |
| D | led-strip-matrix.yaml | 119 [M6][M7][M8]
124 [M6][M7][M8]
134 [M8][M7][M6]
139 [M8][M7][M6]
147 [M6][M7][M8]
152 [M6][M7][M8]
|
