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/Zephyr-latest/dts/bindings/cpu/
Darm,cortex-m1.yaml4 description: ARM Cortex-M1 CPU
6 compatible: "arm,cortex-m1"
/Zephyr-latest/samples/drivers/led/led_strip/boards/
Dthingy52_nrf52832.overlay4 * - M1.S connected to GND
5 * - SDOUT connected to M1.D
6 * - ~300 ohm resistor between M1.D and TP5 (5V / Vbus)
/Zephyr-latest/boards/digilent/arty_a7/doc/
Dindex.rst27 ARM Cortex-M1/M3 DesignStart FPGA
32 both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
37 For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
48 hardware features of the Cortex-M1 reference design:
65 The default configuration for the Cortex-M1 can be found in the defconfig file:
85 The Cortex-M1 reference design is configured to use the 100 MHz external
101 (SWD) capable debug probe connected to the ARM Cortex-M1 CPU.
114 using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA
163 for the Cortex-M1 reference design:
185 the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the
/Zephyr-latest/drivers/modem/
DKconfig.simcom-sim708062 bool "Cat-M1"
64 Enable Cat-M1 mode.
/Zephyr-latest/boards/digilent/arty_a7/
Darty_a7_designstart_fpga_cortex_m1.dts12 model = "Digilent Arty A7 ARM DesignStart Cortex-M1";
20 compatible = "arm,cortex-m1";
Darty_a7_designstart_fpga_cortex_m1.yaml2 name: Digilent Arty A7 ARM DesignStart Cortex-M1
Dboard.cmake5 board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load")
/Zephyr-latest/dts/bindings/display/
Dled-strip-matrix.yaml117 [M0][M1][M2]
122 [M0][M1][M2]
132 [M2][M1][M0]
137 [M2][M1][M0]
149 [M0][M1][M2]
154 [M0][M1][M2]
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnucleo_f767zi.overlay31 "M1",
50 m1-gpios = <&mikroe_stepper_gpios 1 0>;
Dmimxrt1060_evk_mimxrt1062_qspi_B.overlay31 "M1",
50 m1-gpios = <&mikroe_stepper_gpios 1 0>;
Dnative_sim.overlay19 m1-gpios = <&gpio3 1 0>;
/Zephyr-latest/dts/bindings/stepper/ti/
Dti,drv8424.yaml23 m1-gpios = <&mikroe_stepper_gpios 1 0>;
53 m1-gpios:
/Zephyr-latest/tests/arch/common/ramfunc/boards/
Darty_a7_designstart_fpga_cortex_m1.overlay9 /* Cortex-M1 DTCM is No-Execute (NX). Use BRAM instead. */
/Zephyr-latest/soc/arm/designstart/
DKconfig.soc14 ARM Cortex-M1 DesignStart FPGA
/Zephyr-latest/subsys/net/lib/ptp/
Dmsg.c474 int ptp_msg_announce_cmp(const struct ptp_announce_msg *m1, const struct ptp_announce_msg *m2) in ptp_msg_announce_cmp() argument
476 int len = sizeof(m1->gm_priority1) + sizeof(m1->gm_clk_quality) + in ptp_msg_announce_cmp()
477 sizeof(m1->gm_priority1) + sizeof(m1->gm_id) + in ptp_msg_announce_cmp()
478 sizeof(m1->steps_rm); in ptp_msg_announce_cmp()
480 return memcmp(&m1->gm_priority1, &m2->gm_priority1, len); in ptp_msg_announce_cmp()
/Zephyr-latest/tests/subsys/llext/src/
Dmovwmovt_ext.c9 * (except Cortex-M0, M0+ and M1, that don't support them)
/Zephyr-latest/tests/drivers/stepper/stepper_api/boards/
Dnucleo_f767zi.overlay26 m1-gpios = <&arduino_header 17 0>;
/Zephyr-latest/tests/drivers/build_all/stepper/
Dgpio.dtsi37 m1-gpios = <&test_gpio 0 0>;
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay19 m1-gpios = <&gpio3 1 0>;
/Zephyr-latest/lib/libc/minimal/source/string/
Dstring.c218 * @return negative # if <m1> < <m2>, 0 if <m1> == <m2>, else positive #
220 int memcmp(const void *m1, const void *m2, size_t n) in memcmp() argument
222 const char *c1 = m1; in memcmp()
/Zephyr-latest/dts/bindings/gpio/
Dadi,max22190-gpio.yaml74 max22190 mode is configured from M0 and M1 pins with
76 MODE| M1| M0| FRAME | CRC | DAISY CHAIN
/Zephyr-latest/drivers/stepper/ti/
Ddrv8424.c36 uint8_t m1: 2; member
100 uint8_t m1_value = data->pin_states.m1; in drv8424_microstep_recovery()
230 data->pin_states.m1 = m1_value; in drv8424_set_micro_step_res()
320 data->pin_states.m1 = 0U; in drv8424_init()
/Zephyr-latest/samples/subsys/smf/smf_calculator/img/
Dsmf_calculator.svg180 ><path fill="none" d="M1 23.975 L169 23.975" clip-path="url(#clipPath4)"
191 ><path fill="none" d="M1 23.975 L189 23.975" clip-path="url(#clipPath5)"
202 ><path fill="none" d="M1 23.975 L189 23.975" clip-path="url(#clipPath5)"
213 ><path fill="none" d="M1 23.975 L339 23.975" clip-path="url(#clipPath6)"
222 ><path fill="none" d="M1 23.975 L219 23.975" clip-path="url(#clipPath7)"
235 ><path fill="none" d="M1 23.975 L289 23.975" clip-path="url(#clipPath8)"
250 ><path fill="none" d="M1 23.975 L189 23.975" clip-path="url(#clipPath5)"
263 ><path fill="none" d="M1 23.975 L159 23.975" clip-path="url(#clipPath9)"
274 ><path fill="none" d="M1 23.975 L929 23.975" clip-path="url(#clipPath10)"
285 ><path fill="none" d="M1 23.975 L159 23.975" clip-path="url(#clipPath9)"
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/Zephyr-latest/boards/rakwireless/rak5010/doc/
Dindex.rst10 with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors.
11 It is built on the Quectel BG96 LTE CAT M1 & NB1 module,
33 - Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS
/Zephyr-latest/lib/libc/minimal/include/
Dstring.h40 extern int memcmp(const void *m1, const void *m2, size_t n);

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