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/Zephyr-latest/samples/subsys/zbus/priority_boost/
Dsample.yaml11 - "I: 0 ---> L1: T1 prio 5"
15 - "I: 1 ---> L1: T1 prio 5"
19 - "I: 2 ---> L1: T1 prio 5"
23 - "I: 3 ---> L1: T1 prio 5"
27 - "I: 4 ---> L1: T1 prio 5"
31 - "I: 5 ---> L1: T1 prio 5"
35 - "I: 6 ---> L1: T1 prio 5"
50 - "I: 0 ---> L1: T1 prio 1"
54 - "I: 1 ---> L1: T1 prio 1"
58 - "I: 2 ---> L1: T1 prio 2"
[all …]
DREADME.rst21 ZBUS_OBSERVERS(l1, ms1, ms2, s1, l2),
63 I: 0 ---> L1: T1 prio 5
72 I: 1 ---> L1: T1 prio 5
81 I: 2 ---> L1: T1 prio 5
88 I: 3 ---> L1: T1 prio 5
95 I: 4 ---> L1: T1 prio 5
101 I: 5 ---> L1: T1 prio 5
107 I: 6 ---> L1: T1 prio 5
144 I: 0 ---> L1: T1 prio 1
153 I: 1 ---> L1: T1 prio 1
[all …]
/Zephyr-latest/scripts/coccinelle/
Dms_timeout.cocci89 expression L1;
92 fn(..., T, L1)
147 expression L1;
151 fn(..., T, L2, L1)
167 , L2, L1)
194 , L2, L1)
/Zephyr-latest/drivers/cache/
DKconfig.andes19 When L2 cache is inclusive of L1, CPU only needs to perform operations
20 on L2 cache, instead of on both L1 and L2 caches.
/Zephyr-latest/arch/arm/core/cortex_a_r/
DKconfig115 bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
118 Control segregation of L1 I/D-Cache ways between Flash and AXIM.
123 int "L1 I-Cache Flash way"
128 Configure L1 I-Cache ways for Flash interface. Default is reset value, all
132 int "L1 D-Cache Flash way"
137 Configure L1 D-Cache ways for Flash interface. Default is reset value,
/Zephyr-latest/drivers/dma/
DKconfig.intel_adsp_hda46 bool "Intel ADSP HDA Host L1 Exit Interrupt"
50 Intel ADSP HDA Host Interrupt for L1 exit.
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu.c219 "[%u] / addr %p / ref L1[%u]: maximum entry count already reached", in arm_mmu_inc_l2_table_entries()
241 "[%u] / addr %p / ref L1[%u]: entry count is already zero", in arm_mmu_dec_l2_table_entries()
255 * L1 and L2 page table entries. Contains plausibility checks.
260 * word converted to the bits / bit fields used in L1 and
393 * be re-configured at run-time, a L1 section entry will be broken
398 * for which L1 section entries are a valid option, shall be marked in
404 * used in the MMU's L1 page table entries.
413 "Unexpected non-zero L1 PTE ID %u for VA 0x%08X / PA 0x%08X", in arm_mmu_l1_map_section()
438 * @brief Converts a L1 1 MB section mapping to a full L2 table
444 * range's attributes/permissions. Therefore, the single L1 page table
[all …]
/Zephyr-latest/doc/connectivity/networking/api/
Dnet_l2.rst148 - L2 -> L1: Methods as :c:func:`ieee802154_send` and several IEEE 802.15.4 net
153 - L1 -> L2: There are several situations in which the driver needs to initiate
154 calls into the L2/MAC layer. Zephyr's IEEE 802.15.4 L1 -> L2 adaptation API
158 MAC (L2) and PHY (L1) whenever reverse information transfer or close co-operation
164 from L1 into L2 are not implemented as methods in :c:struct:`ieee802154_radio_api`
168 of the L1 -> L2 "inversion-of-control" adaptation API.
172 within the PHY (L1) layer implemented independently of any specific L2 stack, see for
/Zephyr-latest/include/zephyr/arch/xtensa/
Dcache.h261 * two different 512MB regions whose L1 cache settings can be
267 * refer to the same memory through the L1 data cache. Data read
275 * @return A pointer to the same object via the L1 dcache
288 * two different 512MB regions whose L1 cache settings can be
294 * refer to the same memory while bypassing the L1 data cache. Data
295 * in the L1 cache will not be inspected nor modified by the access.
300 * @return A pointer to the same object bypassing the L1 dcache
/Zephyr-latest/drivers/eeprom/
DKconfig.stm3211 Enable EEPROM support on the STM32 L0, L1 family of processors.
/Zephyr-latest/dts/arm/st/l1/
Dstm32l151.dtsi7 #include <st/l1/stm32l1.dtsi>
Dstm32l152.dtsi11 #include <st/l1/stm32l151.dtsi>
Dstm32l151X8-a.dtsi8 #include <st/l1/stm32l151.dtsi>
Dstm32l151Xb-a.dtsi8 #include <st/l1/stm32l151.dtsi>
Dstm32l151Xb.dtsi8 #include <st/l1/stm32l151.dtsi>
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h49 /* L1 init */
63 /* The number of set associative cache way supported on L1 Data Cache */
65 /* The number of set associative cache way supported on L1 Instruction Cache */
/Zephyr-latest/dts/bindings/adc/
Dst,stm32f4-adc.yaml8 like F2, F7 or L1.
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dasm_memory_management.h25 * HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or
26 * L1 SRAM)
/Zephyr-latest/include/zephyr/
Dirq_multilevel.h32 uint32_t l1: CONFIG_1ST_LEVEL_INTERRUPT_BITS; member
56 return irq.bits.l1; in _z_l1_irq()
143 .l1 = 0, in irq_to_level_2()
217 .l1 = 0, in irq_to_level_3()
359 z_irq.bits.l1 += val; in irq_increment()
/Zephyr-latest/samples/subsys/zbus/priority_boost/src/
Dmain.c11 ZBUS_CHAN_DEFINE(chan_a, int, NULL, NULL, ZBUS_OBSERVERS(l1, ms1, ms2, s1, l2), 0);
105 LOG_INF("%d ---> L1: T1 prio %d", *((int *)zbus_chan_const_msg(chan)), in l1_callback()
108 ZBUS_LISTENER_DEFINE(l1, l1_callback);
/Zephyr-latest/arch/xtensa/core/
DREADME_MMU.txt20 Like the L1 cache, the TLB is split into separate instruction and data
162 top-level "L1" page containing the mappings for the page table
171 2. Pin the L1 page table PTE into the data TLB. This creates a double
232 the statically allocated array of L1 page table pages.
246 the L1 data cache on the CPU. If the physical memory storing page
252 lets the L1 data cache act as a "L2 TLB" for applications with a lot
257 But it is also important to note that the L1 data cache on Xtensa is
/Zephyr-latest/boards/st/stm32l1_disco/
Dstm32l152c_disco.dts8 #include <st/l1/stm32l152Xc.dtsi>
9 #include <st/l1/stm32l152r(6-8-b)tx-pinctrl.dtsi>
Dstm32l1_disco.dts8 #include <st/l1/stm32l151Xb.dtsi>
9 #include <st/l1/stm32l152r(6-8-b)tx-pinctrl.dtsi>
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h79 /* L1 init */
93 /* The number of set associative cache way supported on L1 Data Cache */
95 /* The number of set associative cache way supported on L1 Instruction Cache */
/Zephyr-latest/drivers/counter/
DKconfig.stm32_rtc16 Tested on STM32 C0, F0, F2, F3, F4, F7, G0, G4, H7, L1, L4, L5, U5 series

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