| /Zephyr-latest/include/zephyr/ |
| D | irq_multilevel.h | 26 /* Zephyr multilevel-encoded IRQ */
27 uint32_t irq; member
39 /* Third level IRQ's interrupt controller */
41 /* IRQ of the third level interrupt aggregator */
42 uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS; member
45 /* Second level IRQ's interrupt controller */
47 /* IRQ of the second level interrupt aggregator */
48 uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS; member
54 static inline uint32_t _z_l1_irq(_z_irq_t irq) in _z_l1_irq() argument
56 return irq.bits.l1; in _z_l1_irq()
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| D | irq_nextlevel.h | 26 unsigned int irq);
29 unsigned int irq, unsigned int prio,
32 unsigned int irq);
46 * @brief Enable an IRQ in the next level.
51 * @param irq IRQ to be enabled.
54 uint32_t irq) in irq_enable_next_level() argument
59 api->intr_enable(dev, irq); in irq_enable_next_level()
63 * @brief Disable an IRQ in the next level.
68 * @param irq IRQ to be disabled.
71 uint32_t irq) in irq_disable_next_level() argument
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | vector.S | 22 * at byte offset 4 * (IRQ line number).
25 * are handled by the addresses right after the IRQ table.
36 j _isr_wrapper /* IRQ 0 */
37 j _isr_wrapper /* IRQ 1 */
38 j _isr_wrapper /* IRQ 2 */
39 j _isr_wrapper /* IRQ 3 */
40 j _isr_wrapper /* IRQ 4 */
41 j _isr_wrapper /* IRQ 5 */
42 j _isr_wrapper /* IRQ 6 */
43 j _isr_wrapper /* IRQ 7 */
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| D | soc.h | 26 * See gen_isr_tables.py for details on the Zephyr multi-level IRQ
31 * @brief Get an IRQ's level
32 * @param irq The IRQ number in the Zephyr irq.h numbering system
33 * @return IRQ level, either 1 or 2
35 static inline unsigned int rv32m1_irq_level(unsigned int irq) in rv32m1_irq_level() argument
37 return ((irq >> 8) & 0xff) == 0U ? 1 : 2; in rv32m1_irq_level()
41 * @brief Level 1 interrupt line associated with an IRQ
43 * Results are undefined if rv32m1_irq_level(irq) is not 1.
45 * @param The IRQ number in the Zephyr <irq.h> numbering system
46 * @return Level 1 (i.e. event unit) IRQ number associated with irq
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_vim.c | 11 #include <zephyr/arch/arm/irq.h>
26 /* Reading IRQVEC register, ACTIRQ gets loaded with valid IRQ values */ in z_vim_irq_get_active()
32 /* Check if the irq number is valid, else return invalid irq number. in z_vim_irq_get_active()
52 void z_vim_irq_eoi(unsigned int irq) in z_vim_irq_eoi() argument
64 void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_vim_irq_priority_set() argument
68 if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || in z_vim_irq_priority_set()
70 LOG_ERR("%s: Invalid argument irq = %u prio = %u flags = %u\n", in z_vim_irq_priority_set()
71 __func__, irq, prio, flags); in z_vim_irq_priority_set()
75 sys_write8(prio, VIM_PRI_INT(irq)); in z_vim_irq_priority_set()
77 irq_group_num = VIM_GET_IRQ_GROUP_NUM(irq); in z_vim_irq_priority_set()
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| D | intc_system_apic.c | 19 #include <zephyr/irq.h>
22 #define IS_IOAPIC_IRQ(irq) ((irq) < z_loapic_irq_base()) argument
29 * based on the given IRQ parameter.
42 * @param irq the virtualized IRQ
46 void z_irq_controller_irq_config(unsigned int vector, unsigned int irq, in z_irq_controller_irq_config() argument
49 __ASSERT(irq <= HARDWARE_IRQ_LIMIT, "invalid irq line"); in z_irq_controller_irq_config()
51 if (IS_IOAPIC_IRQ(irq)) { in z_irq_controller_irq_config()
52 z_ioapic_irq_set(irq, vector, flags); in z_irq_controller_irq_config()
54 z_loapic_int_vec_set(irq - z_loapic_irq_base(), vector); in z_irq_controller_irq_config()
59 * @brief Enable an individual interrupt (IRQ)
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| D | intc_swerv_pic.c | 17 #include <zephyr/irq.h>
18 #include <zephyr/arch/riscv/irq.h>
57 void swerv_pic_irq_enable(uint32_t irq) in swerv_pic_irq_enable() argument
61 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_enable()
66 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 1); in swerv_pic_irq_enable()
70 void swerv_pic_irq_disable(uint32_t irq) in swerv_pic_irq_disable() argument
74 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_disable()
79 swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 0); in swerv_pic_irq_disable()
83 int swerv_pic_irq_is_enabled(uint32_t irq) in swerv_pic_irq_is_enabled() argument
85 if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) { in swerv_pic_irq_is_enabled()
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| D | intc_eirq_nxp_s32.c | 10 #include <zephyr/irq.h>
67 uint8_t irq; in eirq_nxp_s32_interrupt_handler() local
74 irq = u64_count_trailing_zeros(mask); in eirq_nxp_s32_interrupt_handler()
79 if (data->cb[irq].cb != NULL) { in eirq_nxp_s32_interrupt_handler()
80 data->cb[irq].cb(data->cb[irq].pin, data->cb[irq].data); in eirq_nxp_s32_interrupt_handler()
87 int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin, in eirq_nxp_s32_set_callback() argument
92 __ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX); in eirq_nxp_s32_set_callback()
94 if ((data->cb[irq].cb == cb) && (data->cb[irq].data == arg)) { in eirq_nxp_s32_set_callback()
98 if (data->cb[irq].cb) { in eirq_nxp_s32_set_callback()
102 data->cb[irq].cb = cb; in eirq_nxp_s32_set_callback()
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| D | intc_nrfx_clic.c | 11 void riscv_clic_irq_enable(uint32_t irq) in riscv_clic_irq_enable() argument
13 nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, true); in riscv_clic_irq_enable()
16 void riscv_clic_irq_disable(uint32_t irq) in riscv_clic_irq_disable() argument
18 nrf_vpr_clic_int_enable_set(NRF_VPRCLIC, irq, false); in riscv_clic_irq_disable()
21 int riscv_clic_irq_is_enabled(uint32_t irq) in riscv_clic_irq_is_enabled() argument
23 return nrf_vpr_clic_int_enable_check(NRF_VPRCLIC, irq); in riscv_clic_irq_is_enabled()
26 void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags) in riscv_clic_irq_priority_set() argument
28 nrf_vpr_clic_int_priority_set(NRF_VPRCLIC, irq, NRF_VPR_CLIC_INT_TO_PRIO(pri)); in riscv_clic_irq_priority_set()
31 void riscv_clic_irq_set_pending(uint32_t irq) in riscv_clic_irq_set_pending() argument
33 nrf_vpr_clic_int_pending_set(NRF_VPRCLIC, irq); in riscv_clic_irq_set_pending()
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-int-map.dtsi | 15 irq = <31>;
16 irq-prio = <2>;
20 irq = <15>;
21 irq-prio = <2>;
31 irq = <47>;
32 irq-prio = <2>;
36 irq = <48>;
37 irq-prio = <2>;
41 irq = <49>;
42 irq-prio = <2>;
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| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | soc_common_irq.c | 12 #include <zephyr/irq.h>
20 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
22 riscv_clic_irq_enable(irq); in arch_irq_enable()
25 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
27 riscv_clic_irq_disable(irq); in arch_irq_disable()
30 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
32 return riscv_clic_irq_is_enabled(irq); in arch_irq_is_enabled()
35 void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_riscv_irq_priority_set() argument
37 riscv_clic_irq_priority_set(irq, prio, flags); in z_riscv_irq_priority_set()
40 void z_riscv_irq_vector_set(unsigned int irq) in z_riscv_irq_vector_set() argument
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| /Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/ |
| D | arm_custom_interrupt.c | 25 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
26 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
30 int irq = 0; in z_soc_irq_init() local
32 for (; irq < CONFIG_NUM_IRQS; irq++) { in z_soc_irq_init()
33 NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); in z_soc_irq_init()
39 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
41 if (irq == sw_irq_number) { in z_soc_irq_enable()
44 NVIC_EnableIRQ((IRQn_Type)irq); in z_soc_irq_enable()
47 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
49 if (irq == sw_irq_number) { in z_soc_irq_disable()
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| /Zephyr-latest/arch/common/ |
| D | multilevel_irq.c | 9 #include <zephyr/irq.h>
22 * @brief Get the aggregator that's responsible for the given irq
24 * @param irq IRQ number to query
26 * @return Aggregator entry, NULL if irq is level 1 or not found.
28 static const struct _irq_parent_entry *get_intc_entry_for_irq(unsigned int irq) in get_intc_entry_for_irq() argument
30 const unsigned int level = irq_get_level(irq); in get_intc_entry_for_irq()
37 const unsigned int intc_irq = irq_get_intc_irq(irq); in get_intc_entry_for_irq()
41 if ((intc->level == level) && (intc->irq == intc_irq)) { in get_intc_entry_for_irq()
49 const struct device *z_get_sw_isr_device_from_irq(unsigned int irq) in z_get_sw_isr_device_from_irq() argument
51 const struct _irq_parent_entry *intc = get_intc_entry_for_irq(irq); in z_get_sw_isr_device_from_irq()
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| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-int-map.dtsi | 19 irq = <7>;
20 irq-prio = <2>;
24 irq = <5>;
25 irq-prio = <2>;
29 irq = <11>;
30 irq-prio = <2>;
34 irq = <35>;
35 irq-prio = <2>;
39 irq = <42>;
40 irq-prio = <2>;
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| /Zephyr-latest/subsys/testsuite/include/zephyr/ |
| D | interrupt_util.h | 25 * returning false, here, implies that the IRQ line is in get_available_nvic_line()
55 zassert_true(i >= 0, "No available IRQ line\n"); in get_available_nvic_line()
60 static inline void trigger_irq(int irq) in trigger_irq() argument
62 printk("Triggering irq : %d\n", irq); in trigger_irq()
67 NVIC_SetPendingIRQ(irq); in trigger_irq()
69 NVIC->STIR = irq; in trigger_irq()
77 static inline void trigger_irq(int irq) in trigger_irq() argument
79 printk("Triggering irq : %d\n", irq); in trigger_irq()
81 /* Ensure that the specified IRQ number is a valid SGI interrupt ID */ in trigger_irq()
82 zassert_true(irq <= 15, "%u is not a valid SGI interrupt ID", irq); in trigger_irq()
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| /Zephyr-latest/include/zephyr/arch/arc/v2/ |
| D | arcv2_irq_unit.h | 31 * APIs themselves are writing the IRQ_SELECT, selecting which IRQ's registers
44 * @param irq IRQ line number
50 int irq, in z_arc_v2_irq_unit_irq_enable_set() argument
56 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_irq_enable_set()
69 void z_arc_v2_irq_unit_int_enable(int irq) in z_arc_v2_irq_unit_int_enable() argument
71 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE); in z_arc_v2_irq_unit_int_enable()
81 void z_arc_v2_irq_unit_int_disable(int irq) in z_arc_v2_irq_unit_int_disable() argument
83 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_DISABLE); in z_arc_v2_irq_unit_int_disable()
95 bool z_arc_v2_irq_unit_int_enabled(int irq) in z_arc_v2_irq_unit_int_enabled() argument
100 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_int_enabled()
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| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | irq.h | 87 void z_soc_irq_enable(unsigned int irq);
88 void z_soc_irq_disable(unsigned int irq);
89 int z_soc_irq_is_enabled(unsigned int irq);
91 #define arch_irq_enable(irq) z_soc_irq_enable(irq) argument
92 #define arch_irq_disable(irq) z_soc_irq_disable(irq) argument
94 #define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq) argument
97 extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
106 #define arch_irq_enable(irq) xtensa_irq_enable(irq) argument
107 #define arch_irq_disable(irq) xtensa_irq_disable(irq) argument
109 #define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq) argument
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| /Zephyr-latest/boards/native/native_posix/ |
| D | irq_ctrl.c | 6 * HW IRQ controller model
27 * irq handler
41 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
75 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
77 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
80 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
82 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
151 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
153 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
156 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
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| /Zephyr-latest/arch/x86/core/intel64/ |
| D | locore.S | 674 * When we arrive at 'irq' from one of the IRQ(X) stubs,
675 * we're on the "freshest" IRQ stack (or the trampoline stack if we came from
689 irq: label
729 * Bump the IRQ nesting count and move to the next IRQ stack.
754 irq_enter_nested: /* Nested IRQ: dump register state to stack. */
852 #define IRQ(nr) vector_ ## nr: pushq $(nr - IV_IRQS); jmp irq macro
854 IRQ( 33); IRQ( 34); IRQ( 35); IRQ( 36); IRQ( 37); IRQ( 38); IRQ( 39)
855 IRQ( 40); IRQ( 41); IRQ( 42); IRQ( 43); IRQ( 44); IRQ( 45); IRQ( 46); IRQ( 47)
856 IRQ( 48); IRQ( 49); IRQ( 50); IRQ( 51); IRQ( 52); IRQ( 53); IRQ( 54); IRQ( 55)
857 IRQ( 56); IRQ( 57); IRQ( 58); IRQ( 59); IRQ( 60); IRQ( 61); IRQ( 62); IRQ( 63)
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | irq.c | 5 #include <zephyr/irq.h>
9 bool intc_mtk_adsp_get_enable(const struct device *dev, int irq);
10 void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val);
44 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
47 if (irq < 32) { in z_soc_irq_enable()
48 xtensa_irq_enable(irq); in z_soc_irq_enable()
50 const struct device *dev = irq_dev(&irq); in z_soc_irq_enable()
52 intc_mtk_adsp_set_enable(dev, irq, true); in z_soc_irq_enable()
56 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
58 if (irq < 32) { in z_soc_irq_disable()
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | irq.h | 18 #include <zephyr/irq.h>
38 extern void arch_irq_enable(unsigned int irq);
39 extern void arch_irq_disable(unsigned int irq);
40 extern int arch_irq_is_enabled(unsigned int irq);
43 extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio,
54 void z_soc_irq_enable(unsigned int irq);
55 void z_soc_irq_disable(unsigned int irq);
56 int z_soc_irq_is_enabled(unsigned int irq);
59 unsigned int irq, unsigned int prio, unsigned int flags);
62 void z_soc_irq_eoi(unsigned int irq);
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| /Zephyr-latest/arch/posix/core/ |
| D | irq.c | 23 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
25 posix_irq_enable(irq); in arch_irq_enable()
28 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
30 posix_irq_disable(irq); in arch_irq_disable()
33 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
35 return posix_irq_is_enabled(irq); in arch_irq_is_enabled()
44 * @param irq IRQ line number
48 * @param flags Arch-specific IRQ configuration flags
52 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in arch_irq_connect_dynamic() argument
56 posix_isr_declare(irq, (int)flags, routine, parameter); in arch_irq_connect_dynamic()
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| /Zephyr-latest/scripts/native_simulator/native/src/ |
| D | irq_ctrl.c | 7 * HW IRQ controller model
26 * irq handler
40 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
71 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
73 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
76 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
78 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
152 void hw_irq_ctrl_disable_irq(unsigned int irq) in hw_irq_ctrl_disable_irq() argument
154 irq_mask &= ~((uint64_t)1<<irq); in hw_irq_ctrl_disable_irq()
157 int hw_irq_ctrl_is_irq_enabled(unsigned int irq) in hw_irq_ctrl_is_irq_enabled() argument
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| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-int-map.dtsi | 19 irq = <7>;
20 irq-prio = <2>;
24 irq = <5>;
25 irq-prio = <2>;
29 irq = <11>;
30 irq-prio = <2>;
34 irq = <35>;
35 irq-prio = <2>;
39 irq = <42>;
40 irq-prio = <2>;
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | riscv_plic.h | 20 * @param irq Multi-level encoded interrupt ID
22 void riscv_plic_irq_enable(uint32_t irq);
27 * @param irq Multi-level encoded interrupt ID
29 void riscv_plic_irq_disable(uint32_t irq);
34 * @param irq Multi-level encoded interrupt ID
37 int riscv_plic_irq_is_enabled(uint32_t irq);
42 * @param irq Multi-level encoded interrupt ID
45 void riscv_plic_set_priority(uint32_t irq, uint32_t prio);
48 * @brief Set IRQ affinity.
50 * @param irq IRQ line.
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