10 #include <zephyr/irq.h>
67 	uint8_t irq;  in eirq_nxp_s32_interrupt_handler()  local
74 		irq = u64_count_trailing_zeros(mask);  in eirq_nxp_s32_interrupt_handler()
79 		if (data->cb[irq].cb != NULL) {  in eirq_nxp_s32_interrupt_handler()
80 			data->cb[irq].cb(data->cb[irq].pin, data->cb[irq].data);  in eirq_nxp_s32_interrupt_handler()
87 int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin,  in eirq_nxp_s32_set_callback()  argument
92 	__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX);  in eirq_nxp_s32_set_callback()
94 	if ((data->cb[irq].cb == cb) && (data->cb[irq].data == arg)) {  in eirq_nxp_s32_set_callback()
98 	if (data->cb[irq].cb) {  in eirq_nxp_s32_set_callback()
102 	data->cb[irq].cb = cb;  in eirq_nxp_s32_set_callback()
103 	data->cb[irq].pin = pin;  in eirq_nxp_s32_set_callback()
104 	data->cb[irq].data = arg;  in eirq_nxp_s32_set_callback()
109 void eirq_nxp_s32_unset_callback(const struct device *dev, uint8_t irq)  in eirq_nxp_s32_unset_callback()  argument
113 	__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX);  in eirq_nxp_s32_unset_callback()
115 	data->cb[irq].cb = NULL;  in eirq_nxp_s32_unset_callback()
116 	data->cb[irq].pin = 0;  in eirq_nxp_s32_unset_callback()
117 	data->cb[irq].data = NULL;  in eirq_nxp_s32_unset_callback()
120 void eirq_nxp_s32_enable_interrupt(const struct device *dev, uint8_t irq,  in eirq_nxp_s32_enable_interrupt()  argument
126 	__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX);  in eirq_nxp_s32_enable_interrupt()
131 		reg_val |= BIT(irq);  in eirq_nxp_s32_enable_interrupt()
133 		reg_val &= ~BIT(irq);  in eirq_nxp_s32_enable_interrupt()
139 		reg_val |= BIT(irq);  in eirq_nxp_s32_enable_interrupt()
141 		reg_val &= ~BIT(irq);  in eirq_nxp_s32_enable_interrupt()
146 	REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq));  in eirq_nxp_s32_enable_interrupt()
147 	REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) | BIT(irq));  in eirq_nxp_s32_enable_interrupt()
150 void eirq_nxp_s32_disable_interrupt(const struct device *dev, uint8_t irq)  in eirq_nxp_s32_disable_interrupt()  argument
154 	__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX);  in eirq_nxp_s32_disable_interrupt()
157 	REG_WRITE(SIUL2_IREER0, REG_READ(SIUL2_IREER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
158 	REG_WRITE(SIUL2_IFEER0, REG_READ(SIUL2_IFEER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
161 	REG_WRITE(SIUL2_DISR0, REG_READ(SIUL2_DISR0) | BIT(irq));  in eirq_nxp_s32_disable_interrupt()
162 	REG_WRITE(SIUL2_DIRER0, REG_READ(SIUL2_DIRER0) & ~BIT(irq));  in eirq_nxp_s32_disable_interrupt()
175 	uint8_t irq;  in eirq_nxp_s32_init()  local
195 	for (irq = 0; irq < CONFIG_NXP_S32_EIRQ_EXT_INTERRUPTS_MAX; irq++) {  in eirq_nxp_s32_init()
196 		if (config->max_filter_counter[irq] < GLITCH_FILTER_DISABLED) {  in eirq_nxp_s32_init()
197 			REG_WRITE(SIUL2_IFMCR(irq),  in eirq_nxp_s32_init()
198 				  SIUL2_IFMCR_MAXCNT(config->max_filter_counter[irq]));  in eirq_nxp_s32_init()
199 			REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) | BIT(irq));  in eirq_nxp_s32_init()
201 			REG_WRITE(SIUL2_IFER0, REG_READ(SIUL2_IFER0) & ~BIT(irq));  in eirq_nxp_s32_init()
216 		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), DT_INST_IRQ_BY_IDX(n, idx, priority), \
219 		irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq));                                       \